RECENTLY, multicarrier modulation techniques, such

IEEE TRANSACTIONS ON CIRCUITS AND SYSTEMS I: REGULAR PAPERS, VOL. 52, NO. 5, MAY 2005 911 New Continuous-Flow Mixed-Radix (CFMR) FFT Processor Using Novel In-Place Strategy Byung G. Jo and Myung H. Sunwoo, Senior Member, IEEE Abstract The paper proposes a new continuous-flow mixed-radix (CFMR) fast Fourier transform (FFT) processor that uses the MR (radix-4/2) algorithm and a novel in-place strategy. The existing in-place strategy supports only a fixed-radix FFT algorithm. In contrast, the proposed in-place strategy can support the MR algorithm, which allows CF FFT computations regardless of the length of FFT. The novel in-place strategy is made by interchanging storage locations of butterfly outputs. The CFMR FFT processor provides the MR algorithm, the in-place strategy, and the CF FFT computations at the same time. The CFMR FFT processor requires only two -word memories due to the proposed in-place strategy. In addition, it uses one butterfly unit that can perform either one radix-4 butterfly or two radix-2 butterflies. The CFMR FFT processor using the 0.18 m SEC cell library consists of 37,000 gates excluding memories, requires only 640 clock cycles for a 512-point FFT and runs at 100 MHz. Therefore, the CFMR FFT processor can reduce hardware complexity and computation cycles compared with existing FFT processors. Index Terms Continuous-flow (CF) fast Fourier transform (FFT), in-place, memory architecture, mixed radix (MR), real-time processing. I. INTRODUCTION RECENTLY, multicarrier modulation techniques, such as orthogonal frequency-division multiplex (OFDM) and discrete multitone (DMT), have received great attention in high-speed data communication systems and have been selected for several communication standards, such as wireless local area network (WLAN) [1], asymmetric digital subscriber line (ADSL) [2], very high-speed digital subscriber line (VDSL) [3], digital audio broadcasting (DAB) [4], digital video broadcasting (DVB) [5], powerline communications (PLC) [6], etc. In multicarrier modulation, data symbols are transmitted in parallel on multiple subcarriers [7]. Multicarrier modulationbased transceivers involve fast Fourier transform (FFT) computations that require a large amount of arithmetic operations. The implementation of an FFT processor is one of the most difficult parts in the realization of OFDM and DMT modems and its hardware complexity is very high [4]. Hence, various FFT processors [8] [18] have been proposed to meet real-time processing requirements and to reduce hardware complexity. Manuscript received January 8, 2004; revised November 13, 2004. This work was supported in part by the NRL (National Research Laboratory) program, in part by the uauto project, in part by the SystemIC2010 Program, and in part by IDEC (IC Design Education Center). This paper was recommended by Associate Editor P. Nilsson. B. G. Jo is with the Agency for Defence Development, Daejeon 305-600, Korea. M. H. Sunwoo is with the School of Electrical and Computer Engineering, Ajou University, Suwon 443-749, Korea (e-mail: sunwoo@ajou.ac.kr). Digital Object Identifier 10.1109/TCSI.2005.846667 For high throughput applications, the pipeline architectures [8] [10] have been proposed. However, the pipeline architectures require processing elements where and represent the length of FFT and the radix, respectively. The pipeline architectures consume relatively large area compared with memory architectures [8]. To achieve smaller area, memory architectures using the radix-2 algorithm that have one or two butterfly units have been proposed in [16] [18]. However, these memory architectures require many computation cycles. Hence, they require a relatively high-frequency clock to accomplish real-time requirements. To reduce the computation cycles, a higher radix algorithm should be used. In practice, the radix-2 algorithm requires four times more computation cycles than the radix-4 algorithm. Thus, the FFT processors [13] [15] using the radix-4 algorithm have been proposed. However, the radix-4 FFT processors cannot process 128, 512, 2048, or 8192-point FFTs since they are not powers of four. To compute FFTs that are not powers of four, the mixed-radix (MR) algorithm should be used. The MR algorithm that uses both the radix-4 and radix-2 can perform fast FFT computations and can process FFTs that are not powers of four. The proposed continuous-flow MR (CFMR) FFT processor [19] using the MR algorithm can perform FFT computations regardless of the length of FFT. To minimize the memory size, the in-place algorithm that stores butterfly outputs at the same memory locations used by inputs to the same butterfly has been proposed in [20]; however, it can handle only the fixed-radix FFT algorithms. The existing processors [21], [22] requires one -word memory since they use the in-place strategy [20]; however, they cannot support the CF FFT. Spiffee [21] using the in-place strategy requires many computation cycles since they use the radix-2 algorithm. The CS2410 processor [22] using the MR algorithm employs the in-place strategy; however, it does not use a memory bank structure that can give a low frequency clock by reading and writing several data values at once. The Jaguar II processor [23] using the MR algorithm uses the memory bank structure; however, Jaguar II requires four -word memories since it does not use the in-place strategy. The proposed CFMR FFT processor uses the proposed in-place algorithm, the MR algorithm, and the memory bank structure, and thus, it can minimize the memory size and give a low frequency clock. For real-time processing, the CF FFT processors [17], [18], [23] have been proposed. The FFT processor [17] uses three -word memories for CF FFT. In contrast, to reduce the memory size, the FFT processor [18] uses only two -word memories. However, they still require many computation cycles and a high-speed clock since they use only the radix-2 1057-7122/$20.00 2005 IEEE

912 IEEE TRANSACTIONS ON CIRCUITS AND SYSTEMS I: REGULAR PAPERS, VOL. 52, NO. 5, MAY 2005 Fig. 1. Dataflow graph of a 16-point radix-4 FFT. algorithm. Jaguar II [23] using the radix-4 algorithm reduces the computation cycles compared with the existing radix-2 FFT processors [17], [18]; however, it requires four -word memories. In contrast, the proposed CFMR FFT processor supports the CF FFT using only two -word memories and the MR algorithm. Hence, the proposed processor can reduce the computation cycles compared with the CF FFT processors [17], [18] and the memory size compared with Jaguar II [23]. As mentioned above, various features are used to improve the performance of FFT processors, such as the CF FFT computations, the MR algorithm, and the in-place strategy. However, the existing FFT processors [21] [23] cannot support all of the MR algorithm, the in-place strategy, and the CF FFT at the same time. In other words, the existing in-place strategy [20] for the multibank memory has been proposed only for the fixed-radix FFT algorithms and the existing CF processor using only two -word memories [18] has been proposed only for the radix-2 algorithm. If the existing in-place strategy applies to the MR algorithm, the processor cannot avoid bank conflicts for the CF computations. This paper proposes the new CFMR FFT processor [19] and introduces the novel in-place strategy without having bank conflicts for the MR algorithm. In addition, the CFMR FFT processor using only two -word memories can reduce the memory size and the proposed in-place strategy supports the CF FFT computations. The gate count of the proposed CFMR FFT processor is only 37 000 and the number of clock cycles is 640 for a 512-point FFT. Therefore, the CFMR FFT processor can reduce hardware complexity and the computation cycles compared with the existing FFT processors [21] [23]. The CFMR FFT processor can reduce the gate count 65% and the number of computation cycles 74% compared with Spiffee [21]. In addition, the CFMR FFT processor can reduce the gate count 5% and the number of computation cycles 75% compared with CS2410 [22] and it can reduce the gate count 87% and the memory size 50% compared with Jaguar II [23]. This paper is organized as follows. Section II shows details of the novel in-place strategy for the MR algorithm and the CF FFT computations, and Section III introduces existing FFT processors and the proposed CFMR FFT processor. Section IV explains the implementation and the performance evaluation. Finally, Section V concludes this paper. Fig. 2. Digit-reversal map of a 16-point radix-4 FFT. II. NOVEL IN-PLACE STRATEGY FOR MIXED-RADIX ALGORITHM This section first explains the existing in-place strategy in [20] for the radix-4 algorithm, and then, introduces the novel in-place strategy for the MR algorithm and the CF FFT computations A. Existing In-Place Strategy for Radix-4 Algorithm The in-place strategy [20] uses only one -word memory for FFT computations since it stores butterfly outputs at the same memory locations used by inputs to the same butterfly. Then, FFT processors using the in-place strategy require only the minimum possible amount of memory, i.e., one memory location for each of the original data [20]. In addition, FFT processors using the in-place strategy and two -word memories can overlap the CF FFT computations with concurrent input and output (I/O). By performing concurrent I/O, it is possible to combine the input and output memories and to accomplish the CF computations using only two -word memories. Fig. 1 shows the dataflow graph using the existing in-place strategy [20] for a 16-point radix-4 FFT. To compute the radix-4 butterfly, four inputs can be read concurrently and four outputs can be written concurrently. For concurrent reads and writes, the memory is partitioned into four banks and then no memory access conflicts exist among four read operations or among four write operations. The existing in-place strategy [20] can provide these concurrent reads and writes without bank conflicts. Column 1 and Column 2 in Fig. 1 indicate the memory bank and address assignments. Since the data is allocated in four banks as shown in Column 1 and Column 2 of Fig. 1, four inputs can be read from different banks and four outputs can be written to different banks in all butterfly operations, i.e., butterflies through.

JO AND SUNWOO: NEW CFMR FFT PROCESSOR 913 Fig. 3. Existing dataflow graph of a 32-point MR FFT. The first incoming symbol is stored in the corresponding memory bank and address of Column 1. After the FFT computation of the first incoming symbol, this computed symbol is read out of the computation memory and the second incoming symbol is stored at the same location concurrently, that is, in the corresponding memory bank and address of Column 2. The arrow in Fig. 1 represents the in-place strategy using the same memory location (Bank 3, Address 3) for the output of the first computed symbol and the input of the second incoming symbol. After reading out of the second computed symbol, the memory bank and address of Column 1 are again assigned to the third incoming symbol. In addition, the fourth incoming symbol is assigned to the memory bank and address of Column 2. As a result, the bank and address of Column 1 and then those of Column 2 can be alternately assigned. By this alternation between Column 1 and Column 2, I/O can be performed concurrently and the input and output memories can be combined. Therefore, the radix-4 algorithm can perform the CF FFT computations using only two -word memories. Fig. 2 shows the digit-reversal map for generating the output order. The output order of the radix-4 FFT is the digit-reversal of the input order as shown in Fig. 2. For example, if Input Order 1 is 12, i.e.,, Output Order 1 is 3, i.e.,. This procedure is represented by the bold under lines in Fig. 1. Then, (Bank 3, Address 3) of Column 1 is the 4th output of the computed symbol and it is assigned to the fourth input of the next incoming symbol. Hence, Output Order 1 and Input Order 2 are the same indicated by the arrow in Fig. 1. In other words, the memory bank and address of Output Order 1 in Fig. 1 are equal to those of Input Order 2. Fig. 3 shows the dataflow graph using the existing in-place strategy [20] for a 32-point MR FFT. In Stage 1 and Stage 2, the radix-4 algorithm is used; in Stage 3, the radix-2 algorithm is used. Column 1 and Column 2 in Fig. 3 indicate the memory bank and address assignments by the in-place strategy [20]. The bank and address generation can be expressed as follows: (1) (2) where the symbol means the modulo-4 addition and n is an odd number. Input Order and Output Order in Fig. 3 are the input and output orders, respectively. After the FFT computations, the computed symbol is read out and the next incoming symbol is stored at the same location concurrently. The arrow in Fig. 3 represents that the same memory location (Bank 1, Address 0) is used for the output of the computed symbol and the input of the next incoming symbol. In contrast with Fig. 2, Output Order 1 is generated by Fig. 4 and has an asymmetric form as shown in Fig. 4. The general reversal procedure can be expressed as follows: For example, if Input Order 1 is 1, i.e.,, Output Order 1 is 16, i.e.,, by Fig. 4 and they are represented by the bold under lines in Fig. 3. As a result, (Bank 1, Address 0) of Column 1 is the 17th output of the computed symbol and is assigned to the 17th input (3)

914 IEEE TRANSACTIONS ON CIRCUITS AND SYSTEMS I: REGULAR PAPERS, VOL. 52, NO. 5, MAY 2005 Fig. 4. Existing reversal map of a 32-point MR FFT. Fig. 6. Proposed general reversal map of a 2 -point MR FFT when n =odd. Fig. 5. Interchanging storage locations of the butterfly outputs. of the next incoming symbol. Hence, as shown in Fig. 3, each input of the next incoming symbol is stored in the corresponding each memory bank and address of Column 2. In practice, the FFT computation of the next incoming symbol cannot be performed because of the bank conflicts. In other words, the FFT computations using Output Order 1 generate the bank conflicts since Output Order 1 has the asymmetric form. For example, Butterfly in Stage 1 on the right-hand side that has four inputs represented by the dotted boxes in Fig. 3 faces the bank conflict since the second and third input data reside in Bank 2. Therefore, the MR FFT computations using the exiting in-place strategy [20] cannot avoid the bank conflicts as in Butterfly. As a result, MR FFT processors using the existing in-place algorithm cannot combine the input and output memories and perform the CF FFT computations using only two memories. B. Novel In-Place Strategy for MR Algorithm To avoid these bank conflicts, we propose a novel in-place strategy. The proposed in-place algorithm is made by interchanging storage locations of butterfly outputs. Fig. 5 shows these interchanges. The storage locations of the second and third outputs of each radix-4 butterfly in Stage 2 and a pair of radix-2 butterflies in Stage 3 are interchanged. These interchanges are performed in all stages except for Stage 1 and this rule is applied to all MR FFTs, such as 128, 512, 2,048, 8,192, 32,768, and 131 072-point FFTs. After these interchanges shown in Fig. 5, the bank conflicts can be resolved and the output order with the asymmetric form in Fig. 4 is converted to the new output order with the symmetric form shown in Fig. 6. Therefore, the proposed in-place strategy resolving bank conflicts can support the concurrent I/O and the CF FFT computations. Fig. 6 represents the proposed general reversal map for the MR algorithm of a -point FFT where is an odd number. The most significant digit, i.e., 2 bits, is exchanged with the least Fig. 7. Bank and address generation scheme of a 2 -point MR FFT. significant digit and the other bits perform the bit-reversal. Fig. 6 can be expressed as follows: Fig. 7 shows the bank and address generation scheme of a -point FFT for storing the incoming symbol. In the bank and address generation scheme, an -bit counter and a tree of modulo-4 additions are used. For bank generation, is exchanged with and all of the counter digits are added by modulo-4 except for the second most significant bit. The address of each memory bank indicated by the dotted box is the higher bits excluding the lower 2 bits of the counter output. Fig. 7 can be expressed as follows (4) (5) (6) where the symbol means the modulo-4 addition. Table I shows the bank and address assignments for a 512-point FFT by Fig. 7. Table I contains the bank assigned to the data and the address assigned within each bank. For example, in case of the 511th input data in Table I, Bank is 1 since is 111 111 111 and the result of the modulo-4

JO AND SUNWOO: NEW CFMR FFT PROCESSOR 915 Fig. 8. New dataflow graph of a 32-point MR FFT. TABLE I BANK AND ADDRESS ASSIGNMENTS FOR A 512-POINT FFT Fig. 9. Proposed reversal map of a 32-point MR FFT. addition is 1 by (5). In addition, the address is 127 by (6), since the higher 7 bits of the counter is. Fig. 8 is an example that shows the new dataflow graph of the in-place strategy for a 32-point MR FFT. The interchanges shown in Fig. 5 are performed in the solid boxes of Stage 2 and Stage 3 in Fig. 8. The proposed in-place strategy converts the reversal with the asymmetric form in Fig. 4 to the reversal with the symmetric form in Fig. 9. By the proposed in-place strategy, Column 1 and Column 2 in Fig. 8 can be alternated as shown in Fig. 1. Hence, the proposed in-place strategy can support the CF FFT computations without bank conflicts. For example, Butterfly that has four inputs represented by the dotted boxes in Fig. 8 can avoid the bank conflicts shown in Fig. 3. In Fig. 8, four inputs of Butterfly are read from each bank and four outputs are stored at the same location without bank conflicts. Fig. 9 shows the proposed MR reversal map with the symmetric form of a 32-point FFT. For example, if Input Order 1 is 1, i.e.,, Output Order 1 is 8, i.e.,, by Fig. 9 and they are represented by the bold under lines in Fig. 8. As a result, (Bank 1, Address 0) of Column 1 is the 9th output of the computed symbol, but it was the 17th output in Fig. 3. As shown in Fig. 8, the next incoming symbol has the new memory bank and address assignments of Column 2 that differ from Fig. 3. Moreover, each of four inputs and outputs can access each different bank without bank conflicts in all butterfly operations. The bit vector of the input order, The bit vector of the output order, is expressed by, is given by (7), by (4) in our strategy (8)

916 IEEE TRANSACTIONS ON CIRCUITS AND SYSTEMS I: REGULAR PAPERS, VOL. 52, NO. 5, MAY 2005 If is again applied to (4) as the input order, the bit vector of the output order,, is given by TABLE II EXISTING OPERATION OF CONTINUOUS FLOW FFT Since is the same as, the proposed strategy can combine the input and output memories and can perform concurrent I/O. In contrast, in the existing in-place strategy [20], the bit vector of the output order,, by (3) is expressed by (9) (10) When is applied to (3) as the input order, is given by (11) As a result, and are not the same. Hence, the existing strategy [20] cannot combine the input and output memories and cannot perform concurrent I/O. If in (8) is applied to (5) for the bank generation, the bank assignment is (12) Since the result of the modulo addition in (5) is the same as the result in (12), the proposed strategy can avoid bank conflicts. However, the existing in-place strategy [20] does not have the same results, and thus, it cannot avoid bank conflicts. We have simulated the proposed in-place strategy in C++. The simulations have been performed for various point FFTs, such as 128, 512, 2,048, 8,192, 32,768, and 131 072-point FFTs. We have thoroughly verified the simulation results of the novel in-place strategy. III. ARCHITECTURE FOR PROPOSED CFMR FFT PROCESSOR This section first analyzes the existing CF FFT processors [17], [18], [23] and proposes the FFT processor that can support the proposed in-place strategy, the MR algorithm, and the CF FFT computations. A. Existing CF FFT Processors The FFT processor using the memory architecture [17] requires three -word memories for the CF implementation. Three memories are used for the input buffer, computation buffer, and output buffer. To reduce the amount of memory size for CF FFT implementation, the processor having only two -word memories was proposed in [18]. However, the architecture [18] is based on the radix-2 algorithm. Hence, it requires many computation cycles and a high clock frequency, even though it uses two radix-2 butterfly units. The memory reduction is achieved by the alternation between decimation in frequency (DIF) and decimation in time (DIT) in the computation of FFTs of successive symbols. The DIF computation has the input in natural order and the output in bit-reversed order, and the DIT computation has the input in bit-reversed order and the output in natural order. By alternating the DIF and DIT, it is possible to combine the input and output buffers, and thus, the processor [18] requires only two -word memories for the CF FFT [18]. Table II shows the operation of the CF FFT for the symbol number 0 to 3. Every input symbol experiences three phases: input, computation, and output. Each one of these phases takes one symbolcycle. While the current input symbol is computed, the previous symbol should be read out and the next symbol should be written at the same memory location. In Table II, C, I/O, NAT, and BR represent computation, concurrent input and output, I/O in the natural order, and I/O in the bit-reversed order, respectively. The I/O mode is NAT if the previous FFT mode was DIT and is BR if the previous FFT mode was DIF. In other words, the I/O mode of the symbol number 1 is BR since the FFT mode of the symbol number 0 was DIF in Memory 1. In addition, the I/O mode of the symbol number 3 is NAT since the FFT mode of the symbol number 2 was DIT in Memory 1. The Jaguar II FFT processor [23] uses the MR algorithm and the memory bank structure. Jaguar II supports the CF FFT computations. However, it does not use the in-place strategy using one -word memory; hence, it requires two -word memories. To realize CF, it uses two more -word memories. Therefore, Jaguar II requires four -word memories that are partitioned into four banks for the CF FFT computations and each bank has 2 read/write ports. The memory is a dominant component in terms of hardware complexity and power consumption [7]. As a result, Jaguar II occupies very large area and consumes large power. B. Proposed CFMR FFT Processor The CFMR FFT processor uses the MR algorithm and the memory bank structure to reduce the computation cycles. Fig. 10 shows the proposed CFMR FFT processor using the novel in-place strategy for CF FFT computations. The CFMR FFT processor uses only the radix-4 DIF algorithm. Fig. 11 shows the architecture to store the data input and to read out the computed FFT data. The input data is stored to each bank by using the bank and address generation scheme shown in Fig. 7. The CFMR FFT processor has two -word memories each of which is partitioned into four banks. Each of the two memories is switched between the computation and concurrent I/O. While the current input symbol is computed from Memory 1, the computed symbol is read out of Memory 2 and the next input symbol is stored concurrently at the same location in Memory 2. In other words, the CFMR FFT processor can overlap the FFT computation cycles with data I/O cycles.

JO AND SUNWOO: NEW CFMR FFT PROCESSOR 917 Fig. 12. Radix-4/2 DIF butterfly unit. Fig. 10. Proposed CFMR FFT processor. Fig. 13. Layout of CFMR FFT processor. Fig. 11. Architecture for data I/O. flies. Fig. 12 shows the proposed radix-4/2 DIF butterfly unit used in the CFMR FFT processor, which calculates four butterfly outputs based on the following equations To perform the in-place strategy for the CF FFT, four butterfly outputs that are written to the memory are interchanged. These interchanges are shown in Fig. 5. The address generation unit shown in Fig. 11 generates four addresses for the in-place FFT computations and one address for the concurrent I/O. Since the CFMR architecture uses the memory partitioned into four banks, four data can be read and written concurrently. The CFMR FFT processor supports various point FFTs and each of the internal word lengths for real and imaginary parts is 16 bits. In addition, to improve the signal to quantization noise ratio (SQNR) of FFT/IFFT results, the CFMR FFT processor employs the block floating-point arithmetic. After the butterfly computations at each stage, the largest butterfly output value is detected. Then, all butterfly inputs of the next stage are scaled down according to the scale factor of the previous stage if necessary. When using the block floating-point arithmetic, all butterfly output values share one single scale factor at each stage. Hence, the block floating-point arithmetic can prevent overflow at each stage and the butterfly outputs are normalized in the range of. The SQNR of the CFMR FFT processor is about 65 db, which is better than 55 db of the CS2461 FFT processor [24]. The CFMR FFT processor uses only one butterfly unit, which can perform either one radix-4 butterfly or two radix-2 butter- (13) (14) (15) (16) where,,, and are butterfly inputs, and,, and are twiddle coefficients. All variables are complex numbers. The proposed butterfly unit has three complex multipliers and eight complex adders regardless of the length of FFT and can support the radix-4 and radix-2 algorithms. By adding four multiplexers to the radix-4 butterfly calculation unit, two radix-2 butterflies using the radix-4 unit can also be calculated at once. Four multiplexers represented by the solid box are used to select either the radix-4 calculation or the radix-2 calculation. Therefore, the proposed butterfly unit calculates either two radix-2 butterflies or one radix-4 butterfly in one clock cycle and does not require additional radix-2 butterfly hardware. However, the existing FFT processors [22], [23] require separately the radix-4 butterfly unit and the radix-2 butterfly unit. The gate count of the proposed radix-4/2 DIF butterfly unit is 32 000. The other two multiplexers represented by the dotted box in Fig. 12 interchange the storage locations of the butterfly outputs for the proposed in-place strategy.

918 IEEE TRANSACTIONS ON CIRCUITS AND SYSTEMS I: REGULAR PAPERS, VOL. 52, NO. 5, MAY 2005 TABLE III PERFORMANCE COMPARISONS IV. IMPLEMENTATION AND PERFORMANCE EVALUATION The CFMR FFT processor has been modeled by VHDL and logic synthesis has been performed using the SAMSUNG 0.18 m SEC cell library by the SYNOPSYS tool. Fig. 13 shows the layout results of the CFMR FFT processor. The CFMR FFT processor using two 4 Kbytes memories supports various point FFTs, such as 64, 256, 512, and 1024-point, and each of the internal word lengths for real and imaginary parts is 16 bits. The memory has a 32-bit word length. The ROM memory for twiddle coefficients is used. The ROM stores all twiddle coefficients. The twiddle factor address can be generated by the simple address generation logic. The same ROM which stores 768 twiddle coefficients is used for smaller transforms, i.e., 64, 256, and 512-point. In addition, the CFMR FFT processor employs the block floating-point arithmetic to improve the SQNR. Table III shows the performance comparisons between the CFMR FFT processor and the existing processors [21] [23]. The CFMR FFT processor consists of 37 000 gates excluding memories and the operating frequency is about 100 MHz. Of course, the operating frequency can be increased by adding pipeline stages. In the CFMR processor, the clock frequency for the FFT computations is higher than the symbol sampling frequency. The FFT computation of one symbol is executed within the completion time of concurrent I/O of one symbol. We used the symbol sampling frequency which is half of the clock frequency. Since the clock frequency is twice of the symbol sampling frequency, the symbol sampling frequency can be easily generated from the clock frequency. The CFMR FFT processor completes a 512-point FFT in 6.6 s. This can satisfy the requirement of the DAB standard (Mode II) in which the 512-point FFT (MR) for one OFDM symbol should be completed in 312 s. In addition, the proposed CFMR FFT processor can be easily applied to higher point FFTs by modifying the address generation unit. Hence, the CFMR FFT processor can be used in various DMT and OFDM systems, such as DAB, VDSL, PLC, DVB, WLAN, etc. The Spiffee processor [21] uses the radix-2 algorithm, one -word memory and two cache memories partitioned into two banks. Spiffee operates on 36-bit complex fixed-point data, i.e., 18-bit real and imaginary parts. Spiffee supports only a 1,024- point FFT and requires about 5,100 cycles for a 1,024-point FFT. The gate count is 115 000. However, Spiffee requires many computation cycles since it uses the radix-2 algorithm. In addition, Spiffee cannot support the CF FFT computations. The CS2410 processor [22] using the TSMC 0.18 m cell library uses the in-place strategy and the single memory architecture. Hence, CS2410 has smaller area compared with the existing FFT processor [23]. CS2410 has 39 000 gates and 4 Kbytes memory, and each of the internal word lengths for real and imaginary parts is 16 bits. However, it requires four times of the computation cycles compared with the proposed CFMR FFT processor since it does not use the multibank memory. For example, CS2410 requires 2,697 cycles for a 512-point FFT, while the CFMR FFT processor requires only 640 cycles. Hence, the CFMR FFT processor can reduce the number of computation cycles by about 75% compared with CS2410 [22]. In addition, the CS2410 cannot support the CF FFT computations. The Jaguar II processor [23] using the MR algorithm supports the CF FFT computations; however, Jaguar II requires four -word memories since it does not use the in-place strategy. Jaguar II has 280 000 gates and four 4 Kbytes memories, and each of the internal word lengths for real and imaginary parts is 16 bits. Hence, Jaguar II consumes large power since it has large area and large memory size. The CFMR FFT processor can reduce the gate count by about 87% and the memory size by 50% compared with Jaguar II [23]. The CFMR FFT processor uses one butterfly unit and the proposed in-place algorithm. The proposed radix-4/2 butterfly unit calculates either one radix-4 butterfly or two radix-2 butterflies, and thus, the CFMR FFT processor can remove one and two radix-2 butterfly units used in [22] and [23], respectively. Hence, the CFMR FFT processor has only 37 000 gates and two -word memories. In addition, it uses only the radix-4 DIF algorithm and supports CF FFT by the proposed in-place strategy, while the existing one [18] uses alternation between the DIF and DIT algorithms. The FFT processor [18] requires more FFT computation cycles than the CFMR FFT processor since it uses the radix-2 algorithm.

JO AND SUNWOO: NEW CFMR FFT PROCESSOR 919 In summary, the CFMR FFT processor can support the MR algorithm, the novel in-place strategy, and the CF FFT computations at the same time. However, existing FFT processors cannot support all of these features at the same time. Therefore, the CFMR FFT processor can reduce the number of computation cycles 74% compared with [21]. In addition, it can reduce the gate count 5% and the number of computation cycles 75% compared with [22] and the gate count 87% and the memory size 50% compared with [23]. In addition, the SQNR of the CFMR FFT processor is about 65 db that is better than 55 db of the CS2461 FFT processor [24] dedicated for IEEE 802.11a and HiperLAN 2. V. CONCLUSION This paper proposed the CFMR FFT processor using the novel in-place algorithm. The proposed in-place strategy realized by interchanging storage locations of butterfly outputs can completely remove the bank conflicts for the MR algorithm. Hence, the CFMR FFT processor using only two -word memories can support the MR algorithm and the CF FFT computations. In addition, the CFMR FFT processor uses only one butterfly unit, which can perform either one radix-4 butterfly or two radix-2 butterflies. The CFMR FFT processor consists of 37 000 gates and 8-kB memory and requires only 640 clock cycles for a 512-point FFT. The operating frequency with the 0.18- m SEC cell library is 100 MHz and the SQNR is about 65 db. Therefore, the CFMR FFT processor can reduce the memory size, gate count, and computation cycles compared with existing FFT processors. The proposed CFMR FFT architecture can be used in various DMT and OFDM systems, such as VDSL, PLC, DAB, DVB, WLAN, etc. [14] K. Nadehara, T. Miyazaki, and I. Kuroda, Radix-4 FFT implementation using SIMD multimedia instructions, in Proc. IEEE Int. Conf. Acoust., Speech, Signal Processing (ICASSP), 1999, pp. 2131 2134. [15] B. S. Son, B. G. Jo, M. H. Sunwoo, and Y. S. Kim, A high-speed FFT processor for OFDM systems, in Proc. IEEE Int. Symp. Circuits Systems (ISCAS), vol. 3, 2002, pp. 281 284. [16] H. F. Lo, M. D. Shieh, and C. M. Wu, Design of an efficient FFT processor for DAB systems, in Proc. IEEE Int. Symp. Circuits Systems (ISCAS ), 2001, pp. 654 657. [17] D. Veithen, P. Spruyt, T. Pollet, M. Peeters, S. Braet, O. V. D. Wiel, and H. V. D. Weghe, A 70 Mb/s variable-rate DMT-based modem for VDSL, in Proc. Int. Solid-State Circuits Conf., 1999, pp. 248 249. [18] R. Radhouane, P. Liu, and C. Modlin, Minimizing the memory requirement for continuous flow FFT implementation: continuous flow mixed mode FFT (CFMM-FFT), in Proc. IEEE Int. Symp. Circuits Systems (ISCAS), vol. I, 2000, pp. 116 119. [19] J. H. Baek, B. S. Son, B. G. Jo, M. H. Sunwoo, and S. K. Oh, A continuous flow mixed-radix FFT architecture with an in-place algorithm, in Proc. IEEE Int. Symp. Circuits Systems (ISCAS), vol. 2, May 2002, pp. 133 136. [20] L. G. Johnson, Conflict free memory addressing for dedicated FFT hardware, IEEE Trans. Circuits Syst. II., Analog Digit. Signal Process., vol. 39, no. 5, pp. 312 316, May 1992. [21] B. M. Baas, A low-power, high-performance, 1024-point FFT processor, IEEE J. Solid-State Circuits, vol. 24, no. 3, pp. 380 387, Mar. 1999. [22] Amphion, CS2410 8-1024 Point FFT/IFFT, Jul. 2001. [23] Drey Enterprise Inc., Jaguar II Variable-Point (8-1024) FFT/IFFT Specification, 1998. [24] Amphion, CS2461 64-Point Block Based FFT/IFFT, July 2001. Byung G. Jo received the B.S. degree and the M.S. degree in electronics engineering from the Ajou University, Suwon, Korea, in 2000 and 2002, respectively. He is currently the Researcher at Agency for Defense Development (ADD), Daejeon, Korea. His current research interests are in the areas of satellite communication systems, architectures, and circuits. REFERENCES [1] Part 11: Wireless LAN Medium Access Control (MAC) and Physical Layer (PHY) Specifications, IEEE Std 802.11a-1999, Sep. 1999. [2] C. L. Wang and C. H. Chang, A novel DHT-based FFT/IFFT processor for ADSL transceivers, in Proc. IEEE Int. Symp. Circuits Syst., 1999, pp. 51 54. [3] VDSL Alliance Draft Standard Proposal, Apr. 1999. [4] J. R. Choi, S. B. Park, D. S. Han, and S. H. Park, A 2048 complex point FFT architecture for digital audio broadcasting system, in Proc. IEEE Int. Symp. Circuits Syst., vol. V, 2000, pp. 693 696. [5] DVB, Framing Structure, Channel Coding and Modulation for Digital Terrestrial Television, ETSI EN 300 744 v1.4.1, Jan. 2001. [6] HomePlug Powerline Alliance, HomePlug 0.5 draft medium interface specification, Nov. 2000. [7] N. Weste and D. J. Skellern, VLSI for OFDM, IEEE Commun. Mag., no. 10, pp. 127 131, Oct. 1998. [8] L. Jia, Y. Gao, and H. Tenhunen, A pipelined shared-memory architecture for FFT processor, in Proc. IEEE 42nd Midwest Symp. Circuits Systems, 1999, pp. 804 807. [9] S. Johansson, S. He, and P. Nilsson, Wordlength optimization of a pipeline FFT processor, in Proc. IEEE 42nd Midwest Symp. Circuits Systems, 1999, pp. 501 502. [10] W. Li and L. Wanhammar, A pipeline FFT processor, in Proc. IEEE Workshop on Signal Processing Syst.(SiPS), Oct. 1999, pp. 654 662. [11] M. K. Rudberg, M. Sandberg, and K. Ekholm, Design and implementation of an FFT processor for VDSL, in Proc. Asia-Pacific Conf. Circuits Syst., 1998, pp. 611 614. [12] J. A. Hidalgo, J. Lopez, F. Aruguello, and E. L. Zapata, Area-efficient architecture for fast Fourier transform, IEEE Trans. Circuits Syst. II., Analog Digit. Signal Process., vol. 46, no. 2, pp. 187 193, Feb. 1999. [13] S. He and M. Torkelson, Design and implementation of a 1024-point pipeline FFT processor, Proc. IEEE Custom Integrated Circuits, pp. 131 134, 1998. Myung H. Sunwoo (S 87 M 89 SM 01) received the B.S. degree in electronic engineering from the Sogang University, Korea, the M.S. degree in electrical and electronics from the Korea Advanced Institute of Science and Technology, Korea, in 1980 and 1982, respectively, and the Ph.D. degree in electrical and computer engineering from the University of Texas at Austin, in 1990. He worked for Electronics and Telecommunications Research Institute (ETRI),Daejeon, Korea from 1982 to 1985 and Digital Signal Processor Operations, Motorola, Austin, TX from 1990 to 1992. Since 1992, he has been a Professor with the School of Electrical and Computer Engineering, Ajou University, Suwon, Korea. In 2000, he was a Visiting Professor in the Department of Electrical and Computer Engineering, the University of California, Davis, CA. He is the Director of the National Research Laboratory sponsored by the Ministry of Science and Technology. His research interests include very large-scale integration architectures, system-on-chip design for multimedia and communications, and application-specific digital signal processing architectures. Dr. Sunwoo has published more than 120 papers in international transactions/journals and conferences and also has 28 patents including five U.S. patents. He served as a Technical Program Chair of the IEEE Workshop on Signal Processing Systems (SIPS) in 2003 and a member of the technical program committee of various international conferences. He has received a number of research awards from the Ministry of Commerce, Industry and Energy, Samsung Electronics, and professional foundations. He served as an Associate Editor for the IEEE TRANSACTIONS ON VERY LARGE SCALE INTEGRATION (VLSI) SYSTEMS (2002 2003) and as a Guest Editor for the Journal of VLSI Signal Processing. Currently, He is a Chair of the IEEE CAS Society of the Seoul Chapter.

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