3μm Silicon Photonics

VTT TECHNICAL RESEARCH CENTRE OF FINLAND LTD 3μm Silicon Photonics OFC 2018, Paper Tu3A.5 Timo Aalto, Matteo Cherchi, Mikko Harjanne, Fei Sun, Markku Kapulainen timo.aalto@vtt.fi silicon.photonics@vtt.fi

VTT Technical Research Center of Finland Ltd. Leading research and technology company in the Nordic countries A state-owned, non-profit limited liability company Expert services for domestic & international customers, including MPW and dedicated runs for Si photonics Contract manufacturing services for small and medium volume by VTT Memsfab Ltd. (incl. Si photonics) >1000 wafers/year Micronova clean room: 150 mm wafers, 2 600 m 2 2

OUTLINE Overview of PIC technologies and foundries Passive 3 µm SOI waveguide components Faraday rotation in 3 µm SOI step towards optical isolator & circulator Monolithic and hybrid integration of active components on 3 µm SOI Path from R&D to volume production Plan to combine the benefits of thick and thin SOI Conclusions 3

Overview of PIC technologies & foundries EICs are dominated by Si technology, but PICs come in many flavors PIC platform should be chosen based on your technological requirements and scale-up plans (integration level, volume) Material Maturity Density Complexity Chips per wafer Foundries MPW Laser SiO 2 (PLC) High Low Low Low/Medium Few No Hybrid SiO x N y High Medium Low Medium None No Hybrid Si 3 N 4 High M/H Medium Medium/High Few Yes Hybrid Silicon High High High High Several Yes Hyb./Heter./Monol. InP High Medium High Medium Several Yes Yes GaAs High Medium Low Medium/High Few No Yes LiNbO 3 High Low Low Low None No No Polymers High Low Low High (roll-to-roll) Few No Hybrid Chalcogenides Low Medium Low N/A None N/A No Germanium Low M/L Low N/A None N/A No SiC Low High Low N/A None N/A No Diamond Low High Low N/A None N/A No 4

Overview of PIC technologies & foundries Even in Si photonics, there is a variety of SOI thicknesses used Services vary from rapid prototyping and MPW runs to volume manufacturing 5

Passive 3 µm SOI waveguide components

Two types of Thick-SOI waveguides Rib waveguides Wavelength independent SM operation (1.2 µm < λ < 6 µm) Propagation loss 0.1 db/cm Small birefringency (Δn eff ~10-3 in 3 µm SOI) Low horizontal index contrast, bend radius >2 mm @3 µm SOI Height ratio limit: h H/2 Width limit: W H 0.3 h / H 1 ( h / H ) 2 1) R. Soref et al., IEEE J. Quantum Electron., 27, pp. 1971-1974 (1991) 7

Two types of Thick-SOI waveguides Rib waveguides Wavelength independent SM operation (1.2 µm < λ < 6 µm) Propagation loss 0.1 db/cm Small birefringency (Δn eff ~10-3 in 3 µm SOI) Low horizontal index contrast, bend radius >2 mm @3 µm SOI Strip waveguides Highly multi-moded Propagation loss ~0.1 db/cm (for fundamental mode) Zero birefringence possible by tuning aspect ratio 1.Metal mirror 2.Rib waveguide 3.TIR mirror 4.Rib-strip converter 5.Vertical taper 9

Polarization independent (strip) waveguides and components Geometrical birefringence can be varied around zero by changing W Low-stress cladding and BOX cause a small offset Zero birefringence in 2.8 µm wide and 3 µm thick waveguide 10

Euler bends: Reducing bending radius by x1000 from millimeters to micrometers Adopting Euler bends from civil engineering to waveguide optics Thick-SOI waveguides allow µm-size bends if mode excitation is well-controlled! R eff = 1.3 µm R min = 0.9 µm Loss < 0.1 db/90 11

Small Euler bends need optimized radius, but larger (>25 µm) bends are trivial Bending loss with >20 µm radius is negligible and within measurement accuracy (±0.02 db/90 ) 12

Passive components from MPW runs Variety of filters, (de)multiplexers, delay lines etc. demonstrated 13

Polarization independent 1x4 AWG 100 GHz ch spacing, 5 nm FSR Polarization dependency <10 GHz Footprint 2x3 mm 2 (MPW run #5) 2-3 db loss 0 R4C1 TE 0 R4C1 TM - 10-10 Transmission (db) - 20-30 Transmission (db) - 20-30 - 40 1540 1545 1550 1555 1560 Wavelength (µm) - 40 1540 1545 1550 1555 1560 Wavelength (µm) 14

Ultra-dense spirals with Euler bends Typical propagation loss 0.15 db/cm including bends "Multicast-enabling Optical Switch design employing Si Buffering and Routing Elements, M. Moralis-Pegios et al., accepted for publication in IEEE Photonics Technol. Lett. "DPSK-Demodulation based on Ultra- Compact micron-scale SOI platform," Proc. OFC 15, paper W2A.14 15

Thicker SOI waveguides tolerate more optical power (with same intensity) Nonlinear effects appear as a function of intensity, which depends on optical power and the cross-section area of the waveguide mode Waveguide core height x width: Waveguide core area Estimated maximum optical power at λ = 1.55 µm 0.22 x 0.45 µm (nanowire) 0.2 µm 2 0.02 W 3 x 1 µm (narrow strip) 3 µm 2 0.3 W 3 x 3 µm (strip/rib) 9 µm 2 0.9 W 3 x 10 µm (wide strip/rib) 30 µm 2 3 W 12 x 10 µm (strip/rib) 120 µm 2 12 W 12 x 20 µm (wide strip/rib) 240 µm 2 24 W 16

Microwave photonics on 3 µm SOI Instantaneous frequency measurement using Kerr nonlinearity in a 35 cm long spiral Waveguide chip fabricated in VTT s MPW run Design and testing at University of Sydney (M. Pagani et al.) Measurement results Future vision for increasing the level of integration 17

Temperature independent components Polymer waveguide sections in 3 µm SOI PIC with opposite TO coefficient to achieve athermal response Feasibility demonstrated in a polymer-soi multiplexer: peak shift below ~0.01 nm/k measurement resolution (fiber movement during T scanning) 18

Faraday rotation in 3 µm SOI

Faraday rotation in 3 µm SOI waveguide Magneto-optic polarization rotation (Verdet constant) in Si is ~15 /T/cm First demonstration with 4 db extinction ratio limited by magnetic field (0.3 T available, 0.5 T optimum) 20

Faraday rotation in 3 µm SOI waveguide Polarization rotation averages to zero in a conventional spiral Conventional spiral 21

Faraday rotation in 3 µm SOI waveguide Polarization rotation averages to zero in a conventional spiral Polarization reflection in the corners allows to produce net rotation Conventional spiral Spriral with polarization reflections 22

Monolithic and hybrid integration of active components on 3 µm SOI

Thermo-optic and electro-optic Top view switches and modulators Implanted heaters and contacts in a Si slab Heaters for >10 khz operation PIN modulation >1 MHz Al n p 24 mw/π 12 db ER Al Al Si p n SiO 2 Cross section 5 mw/π 7 db ER 24

Ge photodiodes on 3 µm SOI Horizontal PIN structure with end-fire coupling from a 3 µm SOI waveguide Slow (MHz) operation suitable for a monitor PD ~2 µm wide Ge PDs have 0.9 A/W responsivity and <10 µa dark current (at both polarizations) Narrower PDs: higher dark current Ge photodetector (Includes ~3 db fiber coupling loss) n-well on Si p-well on Ge n-well on Si 3 µm SOI WG 25

Hybrid integration of active components Lasers, amplifiers, modulators and photodetectors have been flip-chip bonded on 3 µm SOI using Au-Au thermo compression bonding 5x5 mm SOI chip with 8-ch SOA and EAM arrays EAM array being tested on SOI InP EAM test result 26

1.3 µm VCSEL light sources High-speed (40 Gbps) layout supports VCSEL integration on SOI Up to 4 mw of single-mode output power Interconnect experiments (without SOI) Open eye at 40 Gb/s after 4.5 km of SMF Power consumption 4.75 pj/bit at 40 Gb/s or 29 fj/bit/km at 28 Gb/s over 20 km of SSMF (ECOC 17, Malacarne) Optical output power Excellent SMSR ~45 db 20 C 80 C 4 mw at RT, 1.2 mw at 80 C 27

VCSEL integration on 3 µm SOI New EU-funded project to integrate VCSELs on 3 µm SOI Up/down reflecting on SOI mirrors to support flip-chip integration Targeting up to 100 Tb/s links www.passion-project.eu Facebook: H2020PASSION Twitter: @PASSIONeuH2020 28

Up/down reflecting mirrors 2 mirror concepts: Down-reflecting TIR mirrors Up-reflecting metal mirrors 2 mirror angles: 54.7 with standard TMAH etch 45 with additional Triton-X 45 o K. Rola et al, Microsyst. Technol. 20 (2014) 221 29

Path from R&D to volume production

Automated wafer-level testing (WLT) Ramping up volume manufacturing requires automated WLT with simultaneous O/E testing Fully automated cassette-to-cassette tool has been taken into use I/O coupling with up-reflecting mirrors and lensed fibers 31

Easy access to MPW and dedicated runs with PDKs Handbooks and example files PDKs in PhoeniX & IPKISS (incl. models for circuit simulation) Evaluation dies 32

MPW runs and epixfab Passive waveguide module with low-loss passive components Additional module with implantation and metals for heaters, PIN modulators, flip-chip etc. Packaging and flip-chip services separately available 1-2 MPW runs per year silicon.photonics@vtt.fi / http://www.vtt.fi/siliconphotonics + 2000 fixed cost per order 5x10 mm chips (x8) 20x20 mm first chip 20x20 mm extra chips Passive chip 6000 6000 +2500 /chip Two chip sizes: 5x10 mm (x8) or 20x20 mm (sold individually) Extra cost for the metallization module +5000 +6000 +2500 /chip Training etc. via epixfab The European Silicon Photonics Alliance Si photonics pilot line expected to launch by 2019 (H2020) 33

Path to small and medium volume manufacturing via VTT Memsfab Ltd. Easy path from R&D at VTT to contract manufacturing at VTT Memsfab Same Micronova fab and same processing tools used Scalability to >1000 wafers/year (~100 SiPh wafers via VTT Memsfab and >100 via VTT in 2017) 34

Plan to combine the benefits of thick and thin SOI

Spot-size converters on 12 µm SOI to couple light into 3 µm SOI PICs Polished facets (wafer-level processing to be developed for volume production) Best measured on-chip losses <1 db for both TE & TM Vertical taper 12 2 µm (+ IR output) IR output of a 3x3 µm downtapered waveguide Pigtailed prototype With 3+12 µm SOI 36

Locally thinned waveguides on 3 µm SOI for high-speed devices and I/O coupling Our plan is to combine the benefits of Thick & Thin SOI on one platform (on-going work) Fiber Optical interposer Inverse taper 3 µm thick waveguide, low-loss, zero-birefringence, Faraday rotation Evanescently coupled III-V devices (lasers, SOAs, EAMs) SIDE VIEW Submicron waveguide: fast detectors and modulators and polarization management 37

Locally thinned waveguides on 3 µm SOI for high-speed devices and I/O coupling Simulated 99.7% coupling efficiency from 3 µm SOI to thin a-si waveguide SiO 2 a-si Si SIDE VIEW SiO 2 Si SiO 2 a- Si TOP VIEW SiO 2 38

Conclusions

CONCLUSIONS 3 µm SOI technology offers SM PICs with low loss and small footprint Polarization independent operation with strip waveguides Athermal operation with short polymer waveguide sections Faraday rotation in 3 µm SOI is a step towards on-chip isolator Presently high-speed (>10 GHz) devices only via hybrid integration Local thinning as a path towards high-speed modulators and PDs Basic process available via MPW runs and documented in PDKs Small/medium volume manufacturing via VTT Memsfab Ltd. 40

Acknowledgments We thank EU, Tekes and industrial partners for funding and all R&D partners for fruitful collaboration RAPIDO-project (EU FP7, grant agreement 619806) OPEC-project (TEKES, grant agreement 2814/31/2015) PASSION project (EU H2020, grant agreement 780326) Contact: timo.aalto@vtt.fi www.vtt.fi/siliconphotonics silicon.photonics@vtt.fi Meet us in OFC 18: Wednesday: www.7pennies.com/news-events/pic-workshop-ofc-2018 Tue-Thu: Hitachi High-Technologies booth #6217 41

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