FABRICATION 3 EXAMPLES Fabrication Example 1 The example shows a 2 D side view of the fabrication steps for the following A single NMOS transistor Metal1 contacts Metal1 layer EEC 116, B. Baas 21 1
Fabrication Patterning of SiO 2 Grow SiO 2 on Si by exposing to O 2 high temperature accelerates this process Cover surface with photoresist (PR) Sensitive to UV light (wavelength determines feature size) Positive PR becomes soluble after exposure Negative PR becomes insoluble after exposure EEC 116, B. Baas Source: CMOS Digital Integrated Circuits 22 Fabrication Patterning of SiO 2 Photoresist removed with a solvent SiO 2 removed by etching (HF) Remaining photoresist removed with another solvent EEC 116, B. Baas Source: CMOS Digital Integrated Circuits 23 2
NMOS Transistor Fabrication Thick field oxide grown Field oxide etched to create area for transistor Gate oxide (high quality) grown EEC 116, B. Baas Source: CMOS Digital Integrated Circuits 24 NMOS Transistor Fabrication Polysilicon deposited (doped to reduce R) Polysilicon etched to form gate Gate oxide etched from source and drain Self aligned process because source/drain aligned by gate Si doped with donors to create n+ regions EEC 116, B. Baas Source: CMOS Digital Integrated Circuits 25 3
NMOS Transistor Fabrication Insulating SiO 2 grown to cover surface/gate Source/Drain regions opened Aluminum evaporated to cover surface Aluminum etched to form metal1 interconnects EEC 116, B. Baas Source: CMOS Digital Integrated Circuits 26 Fabrication Example 2 The example shows a 3 D view of the fabrication steps for the following A CMOS inverter A single NMOS transistor A single PMOS transistor Metal1 contacts Metal1 layer EEC 116, B. Baas 27 4
Inverter Fabrication Inverter Logic symbol CMOS inverter circuit CMOS inverter layout (top view of lithographic masks) EEC 116, B. Baas 28 Inverter Fabrication N wells created Thick field oxide grown surrounding active regions Thin gate oxide grown over active regions EEC 116, B. Baas Source: CMOS Digital Integrated Circuits 29 5
Inverter Fabrication Polysilicon deposited Chemical vapor deposition(places the Poly) Dry plasma etch(removes unwanted Poly) EEC 116, B. Baas Source: CMOS Digital Integrated Circuits 30 Inverter Fabrication N+ and P+ regions created using two masks Source/Drain regions Substrate contacts EEC 116, B. Baas Source: CMOS Digital Integrated Circuits 31 6
Inverter Fabrication Insulating SiO 2 deposited using CVD Source/Drain/Substrate contacts exposed EEC 116, B. Baas Source: CMOS Digital Integrated Circuits 32 Inverter Fabrication Metal (Al) deposited using evaporation Meta1 contacts made with Aluminum here Metal patterned by etching EEC 116, B. Baas Source: CMOS Digital Integrated Circuits 33 7
Fabrication Example 3 The example shows a 2 D side view of the fabrication steps for the following A CMOS inverter A single NMOS transistor A single PMOS transistor Metal1 contacts Metal1 layer Metal2 vias Metal2 EEC 116, B. Baas 34 CMOS Process Walk-Through p-epi p+ (a) Base material: p+ substrate with p-epi layer p-epi p+ SiN 3 4 SiO 2 (b) After deposition of gate-oxide and sacrificial nitride (acts as a buffer layer) p+ (c) After plasma etch of insulating trenches using the inverse of the active area mask EEC 116, B. Baas Source: Digital Integrated Circuits, 2nd 35 8
CMOS Process Walk-Through SiO 2 (d) After trench filling, CMP planarization, and removal of sacrificial nitride n (e) After n-well and V Tp adjust implants p (f) After p-well and V Tn adjust implants EEC 116, B. Baas Source: Digital Integrated Circuits, 2nd 36 CMOS Process Walk-Through poly(silicon) (g) After polysilicon deposition and etch n+ p+ (h) After n+ source/drain and p+source/drain implants. These steps also dope the polysilicon. SiO 2 (i) After deposition of SiO 2 insulator and contact hole etch. EEC 116, B. Baas Source: Digital Integrated Circuits, 2nd 37 9
CMOS Process Walk-Through Al (j) After deposition and patterning of first Al layer. Al SiO 2 (k) After deposition of SiO 2 insulator, etching of via s, deposition and patterning of second layer of Al. EEC 116, B. Baas Source: Digital Integrated Circuits, 2nd 38 ADVANCED METAL INTERCONNECT EXAMPLES 10
Four Levels of Metal Example EEC 116, B. Baas Source: Digital Integrated Circuits, 2nd 40 Advanced Metallization EEC 116, B. Baas Source: Digital Integrated Circuits, 2nd 41 11
Microprocessor Interconnect m8 Future microprocessor interconnect 8 levels of metal Steadily increasing pitch and thickness with higher levels for higher performance m7 m6 m5 m4 m3 m2 m1 Source: IBM EEC 116, B. Baas 42 Source: ITRS Interconnect, 2005 ASIC Interconnect m8 Future Application Specific IC (ASIC) interconnect 8 levels of metal More regular structure Semi global is 2x Intermediate pitch Global is 4x Intermediate pitch m7 m6 m5 m4 m3 m2 m1 Source: IBM EEC 116, B. Baas 43 Source: ITRS Interconnect, 2005 12
IBM 90 nm 64 bit microprocessor (1) Al(Cu) [top] (2) 6x Cu (3) 2x Cu (5) 1x Cu (1) W local [bottom] 0.12 μm width & spacing Source: IBM EEC 116, B. Baas 44 13