VTT silicon photonics driving new business growth in Finland

Transcription

1 VTT silicon photonics driving new business growth in Finland Timo Aalto Research Team Leader 30/11/2018 VTT beyond the obvious 1

2 What is silicon photonics? Generating, manipulating, guiding and using light In Photonic Integrated Circuits (PICs) processed on silicon-on-insulator (SOI) wafers Primarily single-mode (SM) components and systems

3 Many open access Si photonics platforms WaveGuide Si SiO 2 Si substrate PSV FiberCoupler ISIPP50G Passive + heaters Si310-PH IHP SG25_PIC IHP SG25H4_EPIC Passives + Heaters + Implanted PIN + Flip-chip Passive + heaters Actives Customized actives & Passives with EBL Photonic BiCMOS 220 nm SOI 310 nm SOI 220 nm SOI 3 µm SOI nm SOI 220/340 nm SOI 220 nm SOI 220 nm SOI 220/300 nm SOI 220 nm SOI

4 Different flavours and functionalities Thick-SOI waveguides Typically 3 µm SOI SM by rib-shape Submicron waveguides Typically nm SOI SM by size Passive PICs Passive waveguides Thermo-optic components Active PICs Modulators Photodiodes Light sources

5 Main application areas for Si photonics Health Care IoT & Autonomous Systems ICT Agri & Food Manufacturing & Industry 4.0 Military & Aerospace Consumer Electronics & Lighting 2500 CH4 C2H6 C2H C2H2 Absorption * 10^ Wavelength, nm 5

6 Photonics integration Why? Discrete components don t scale up well into complicated systems Ludwig-Maximilians-University Munich

7 Combination of rib and strip waveguides Keeping light in the fundamental mode Ultra-wide wavelength range (1.2-6 µm) Ability to propagate high optical powers (>1 W) Ultra high confinement Small db/cm loss for both waveguides Zero birefringence in (square) strip waveguides Si Si Thicker SOI has reduced sensitivity to linewidth and SOI thickness variations

8 Why SOI thickness and etch depth still need precise control? SM condition Directional couplers Si pedestals We use bonded SOI wafers with ion-beam-trimming Top-view of optical coupling: Target SOI pedestal 200 nm 40% etch (target) 50% etch 33% etch A. Haapalinna and T. Aalto, IEEE S3S Conference, San Francisco, Oct 2017

9 Small bends and mirrors for dense PICs Total internal reflection mirrors: db loss in negligible footprint Euler bends were a breakthrough: Negligible loss in small footprint 5 µm

10 Wavelength (de)multiplexers Echelle gratings Asymmetric Mach-Zehnder interferometers Polarization independent 1x4 AWG: 100 GHz ch spacing, 5 nm FSR Polarization dependency <10 GHz 2-3 db loss 1x4 AWG Footprint 2x3 mm 2 TE TM Square waveguide

11 Modulators, switches and photodetectors Implanted heaters and contacts Heaters for >10 khz operation PIN modulation >1 MHz Ge photodiodes Ge photodetector 3 µm SOI waveguide Al Si p SiO 2 Cross 5 mw/π n 24 mw/π (no underetch) n-well on Si p-well on Ge n-well on Si

12 Hybrid integration of active components Lasers, amplifiers, modulators and photodetectors have been flip-chip bonded on 3 µm SOI using Au-Au thermo compression bonding 5x5 mm SOI chip with 8-ch SOA and EAM arrays EAM array being tested on SOI InP EAM test result

13 Hybrid VCSEL integration on 3 µm SOI VCSEL-SOI coupling with up-reflecting mirrors Measured mirror losses ~0.5 db PIC layout (2x2 cm) TE Mirror output TM 50 Gb/s 2 Tb/s

14 Automated wafer-level testing (WLT) Ramping up volume manufacturing requires automated WLT with simultaneous O/E testing Fully automated cassette-to-cassette tool set up in Micronova I/O coupling with up-reflecting mirrors and lensed fibers

15 Microwave photonics on 3 µm SOI Instantaneous frequency measurement using Kerr nonlinearity in a 35 cm long spiral Design and testing at University of Sydney (M. Pagani et al.) Measurement results Future vision for increasing the level of integration

16 Next R&D steps in 3 µm SOI 1. Low-loss, low-cost coupling from 3 µm SOI to SSMF arrays 3 µm SOI chip 12 µm SOI interposer Pigtailed prototype with 3 µm SOI PIC and 12 µm SOI interposer Vertical taper 12 2 µm (+ IR output)

17 Next R&D steps in 3 µm SOI 1. Low-loss, low-cost coupling from 3 µm SOI to SSMF arrays 2. High-speed modulators and photodetectors Fiber Integrated SSC 3 µm thick waveguide (low-loss, zero-birefringence) Evanescently coupled III-V devices (lasers, SOAs, EAMs) SIDE VIEW Thin a-si waveguide pulling light to the surface Fast (monolithic) detectors and modulators

18 Next R&D steps in 3 µm SOI 1. Low-loss, low-cost coupling from 3 µm SOI to SSMF arrays 2. High-speed modulators and photodetectors 3. Monolithically integrated isolator and circulator

19 Next R&D steps in 3 µm SOI 1. Low-loss, low-cost coupling from 3 µm SOI to SSMF arrays 2. High-speed modulators and photodetectors 3. Monolithically integrated isolator and circulator 4. Single-photon detectors and nonlinear PICs for quantum photonics DOI /ncomms cudos/facilities/quantum-photonics.shtml

20 Next R&D steps in 3 µm SOI 1. Low-loss, low-cost coupling from 3 µm SOI to SSMF arrays 2. High-speed modulators and photodetectors 3. Monolithically integrated isolator and circulator 4. Single-photon detectors and nonlinear PICs for quantum photonics 5. Wafer-level packaging and photonics-electronics integration MOD1 Test Board

21 Growth potential in silicon photonics SiPh staff & revenue in Finland Compared to ICs, PIC technology is just starting to grow In Thick-SOI we have some unique knowhow and competence in Finland We have all that is needed to scale the SiPh revenue in Finland to >100 M by 2030 This was the hype Continued growth Saturation? Hype?

22 Some project consortia OPEC RAPSI

23 Thank #VTTbeyondtheobvious 30/11/2018 VTT beyond the obvious 23