Efficient FFT Network Testing and Diagnosis Schemes

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1 IEEE TRANSACTIONS ON VERY LARGE-SCALE INTEGRATION (VLSI) SYSTEMS, VOL. 10, NO. 3, JUNE Efficient FFT Network Testing and Diagnosis Schemes Jin-Fu Li and Cheng-Wen Wu, Senior Member, IEEE Abstract We consider offline testing, design-for-testability, and diagnosis for fast Fourier transform (FFT) networks. A practical FFT chip can contain millions of gates, so effective testing and fault-tolerance techniques usually are required in order to guarantee high-quality products. We propose M-testability conditions for FFT butterfly, omega, and flip networks at the double-multiply subtract add (DMSA) module level. A novel design-for-testability technique based on the functional bijectivity property of the specified modules to detect faults other than the cell faults is presented. It guarantees 100% combinational fault coverage with negligible hardware overhead about 0.17% for an FFT network with 16-bit operand words, independent of the network size. Our design requires fewer test vectors compared with previous ones a factor of up to 1 (6 2 5 ), where is the word length. We also propose C-diagnosability conditions and a C-diagnosable FFT network design. By properly exchanging and blocking certain fault propagation paths, a faulty DMSA module can be located using a two-phase deterministic algorithm. The blocking mechanism can be implemented with no additional hardware. Compared with previous schemes, our design reduces the diagnosis complexity from ( ) to (1). For both testing and diagnosis, the hardware overhead for our approach is only about 0.43% for 16-bit numbers regardless of the FFT network size. Index Terms Butterfly network, C-testable, design-for-diagnosability, design-for-testability, diagnosis, fault tolerance, fast Fourier transform (FFT), logic testing, M-testable. I. INTRODUCTION FAST Fourier transform (FFT) algorithms are used in a wide range of digital-signal-processing (DSP) applications, such as digital filtering, correlation, speech and audio coding, image processing, digital broadcasting, and spectrum analysis [1] [3]. Due to the inherent parallelism of FFT algorithms, FFT networks are often used in real-time processing or where speed is of extreme importance. A typical -point FFT network is composed of two-input butterflies, organized as stages where each stage includes butterflies. For example, an eight-point FFT butterfly network is shown in Fig. 1. Although, in practice can be very large, with the advent of deep-submicron VLSI technology and system-on-chip design methodology, we have seen the possibility of integrating a large FFT network on a single chip [4] [9]. Limited accessibility of the circuit components in such a chip, however, poses considerable challenges in testing and diagnosis. Particularly, the cost of diagnosis is rapidly increasing along with the complexity of the chip. It is Manuscript received January 13, 2001; revised July 9, The authors are with the Laboratory for Reliable Computing (LARC), Department of Electrical Engineering, National Tsing Hua University, Hsinchu, Taiwan ( cww@ee.nthu.edu.tw). Publisher Item Identifier S (02) Fig. 1. An eight-point FFT network. indispensable to control these costs and provide a cost-effective solution. Therefore, it is important to develop efficient testing and diagnosis approaches. Diagnosis is the prerequisite for repair. It also plays an important role in identifying design and process errors. For big FFT chips, therefore, diagnosis is vital for yield improvement. Diagnosis is also the key to many fault tolerance approaches that improve product reliability. To improve the testability and diagnosability of FFT chips, several testable or diagnosable designs have been proposed [10] [23]. Jou and Abraham [10], introduced a concurrent error-detection (CED) scheme for FFT networks, whose hardware overhead ratio is. A time-redundancy method was also used to detect and locate the faulty modules. In [11], a recomputing by alternate path approach was proposed to detect errors during normal operation. Once an error is found, the faulty butterfly module is located within extra cycles. A one-pass procedure derived from an algorithmic flow allows detection and location of single faults [13]. The procedure needs operations for an -point FFT network. In [14], an approach for CED and fault location in homogeneous VLSI/WSI architectures for computing complex FFT was presented. Tao and Hartmann [16] developed a CED method using 5% extra hardware and less extra time delay than the scheme proposed in [10]. Also, the fault coverage was significantly increased. In [17], the butterfly networks were shown to be testable with only 32 test patterns by using a novel input-assignment technique. The proposed test scheme guarantees 100% coverage of combinational single-cell faults. Then, in /02$ IEEE

2 268 IEEE TRANSACTIONS ON VERY LARGE-SCALE INTEGRATION (VLSI) SYSTEMS, VOL. 10, NO. 3, JUNE 2002 [18], C-testability conditions and technique guaranteeing 100% single module-fault coverage for FFT networks were presented. The hardware overhead is about 0.47% for 8-bit inputs. Feng and Lombardi [15] also proposed a C-testable FFT design using the topological equivalence scheme, which requires test vectors, where represents the number of all inputs combinations of a two-point butterfly module. A testing and fault location process with time complexity was also developed. Later, concurrent error location and correction methods for FFT networks were proposed [20], where a faulty component can be located with an extra try followed by comparisons of corrupted outputs. An algorithm-based CED scheme using the checksum approach was reported in [21], which allows high-error coverage with low false alarm rate by applying the linear weight factors to the checksums. In [23], a CED scheme for FFT perfect-shuffle network was proposed. This scheme can locate a pair of faulty butterfly modules without additional computations and the faulty pair can be replaced by a spare one as soon as a fault is detected. In this paper, we configure the FFT networks as iterative logic arrays (ILAs) to greatly improve their testability and diagnosability. We propose M-testability conditions for FFT butterfly, omega, and flip networks at the double-multiply-subtract-add (DMSA) module level. A novel design-for-testability technique based on the functional bijectivity property of the DMSA module to detect faults other than the cell faults is presented. Our method guarantees 100% combinational fault coverage with negligible hardware overhead about 0.17% for an FFT network with 16-bit operand words, independent of the network size. Our design requires fewer test vectors compared with previous ones a factor of up to, where is the word length. We also propose C-diagnosability conditions and a C-diagnosable FFT network design. By properly exchanging and blocking certain fault propagation paths, a faulty DMSA module can be located using a two-phase deterministic algorithm. The blocking mechanism can be implemented without additional hardware. Compared with previous schemes, our design reduces the diagnosis complexity from to. For both testing and diagnosis, the hardware overhead is only about 0.43% for 16-bit numbers regardless of the FFT network size. II. BACKGROUND A. FFT The discrete FFT of a sequence of length is [1] where The term represents the twiddle factor. Algorithms that decompose the computation of the discrete Fourier transform of a length into continuously smaller discrete Fourier transform are called FFT algorithms [1]. An -point FFT can be implemented with hardware by a -stage butterfly network. The (1) (2) Fig. 2. A butterfly constructed with four MSA modules. basic butterfly module performs a two-point butterfly computation, where the complex values and are computed according to the following equations: The factor is a representative twiddle factor. Complex multiplication, addition, and subtraction operations are required in the butterfly module. The entire FFT is finished in cycles with butterfly modules. Let,, and be expressed in complex form as follows: where. Substituting (4) into (3), we obtain The computation in (5) can be implemented by four identical multiply subtract add (MSA) modules, as shown in Fig. 2 [12], [24]. Each MSA module is composed of a parallel 2 s-complement array multiplier, a binary subtractor, and a binary adder. A bit-level array design of the MSA module is shown in Fig. 3 [22]. The array size is for -bit numbers. In this design, three types of cell are used: a) the multiplier cell ( ), b) the subtractor cell ( ), and c) the adder cell ( ), as shown in Fig. 4. B. M-Testable ILAs We follow the definitions given in [25]. A regular array composed of identical cells is called an iterative logic array (ILA). Each cell in an ILA performs a combinational function :, where and for. A cell function is injective if,. If a function is injective and, then the function (3) (4) (5)

3 LI AND WU: EFFICIENT FFT NETWORK TESTING AND DIAGNOSIS SCHEMES 269 Fig D+45 tessellation. Fig. 3. The bit-level array design for an MSA module. Fig. 6. Testable butterfly design using an additional switch. Fig. 4. (a) Multiplier cell. (b) Subtractor cell. (c) Adder cell. is bijective.acomplete or exhaustive input sequence for a cell is an input sequence including all input combinations of the cell. A complete output sequence is defined analogously. A shortest complete sequence is called a minimal complete sequence. To test an ILA based on the single cell fault model, it is sufficient to verify the function of every cell in it. An ILA is C-testable [26] if it can be tested with a constant number of test vectors regardless of the array size (or number of cells). An M-testable array is a C-testable array which is testable with the minimal constant number of vectors [27]. M-testability implies that the array can be pseudoexhaustively tested with only patterns regardless of the array size, where is the word length of the cell. It has been shown that a -dimensional ILA,, is M-testable if it has a bijective cell function [25], [27]. For example, consider the two dimensional (2-D) mesh-connected array as shown in Fig. 5 [25], where denotes a minimal complete input sequence. The cells lie on the same diagonal line apparently receive the same minimal complete input sequence if the cell function is bijective and we apply the primary input sequences to the boundary cells as shown in the figure. This pattern is called a tessellation [28]. Since the cell function is bijective, any fault can automatically be propagated to some observable primary outputs. If the cell function is not bijective, then a design-for-testability technique can be used to modify the cell function to make it bijective [29].

4 270 IEEE TRANSACTIONS ON VERY LARGE-SCALE INTEGRATION (VLSI) SYSTEMS, VOL. 10, NO. 3, JUNE 2002 Fig. 7. An eight-point FFT network composed of DMSA1 and DMSA2 networks in test mode. III. M-TESTABLE FFT NETWORKS A. M-Testability Conditions for FFT Networks A butterfly is composed of four MSA modules as shown in Fig. 2. We add a switch to the input of the butterfly for exchanging and, as shown in Fig. 6. The butterfly can be partitioned into two double-msa (DMSA) modules, DMSA1 and DMSA2, in the test mode, where DMSA1 and DMSA2 represent, respectively, the upper and lower MSA pairs in Fig. 6. An -point FFT network thus can be viewed as formed by the separate DMSA1 and DMSA2 networks. For example, the eight-point FFT butterfly network in test mode is as shown in Fig. 7. In test mode, the functions of DMSA1 are and the functions of DMSA2 are (6) Fig. 8. An M-testable 16-point FFT butterfly network. From (6) and (7), we see that DMSA1 and DMSA2 have bijective functions if and, i.e., and. The M-testability condition for an -point FFT butterfly network based on the DMSA1 (DMSA2) is described in thm 1 (see Appendix I-A for its proof). In what follows, we assume that for some. Theorem 1: An -point FFT butterfly network based on the DMSA1 (DMSA2) module is M-testable if the outputs of the (7) bottom-left DMSA1 (DMSA2) module in each four-point FFT block are swapped and the function of the DMSA1 (DMSA2) module with ( ) is changed to that of DMSA2 (DMSA1), where. According to Thm 1, an M-testable 16-point FFT butterfly network, as depicted in Fig. 8, can be obtained. During the test mode, the DMSA2 modules with are changed to DMSA1 modules, and the DMSA1 modules with are changed to DMSA2 modules. Also, the outputs of the bottom-left module of each four-point block (e.g.,,,, and ) are swapped. The M-testability conditions for -point FFT omega and flip networks are described in Thms 2 and 3, respectively. The proofs are given in Appendix I-A. Examples of M-testable

5 LI AND WU: EFFICIENT FFT NETWORK TESTING AND DIAGNOSIS SCHEMES 271 B. Design for M-Testability As stated in the previous theorems, the prerequisite for M-testability is the realization of the exchange function and output swapping mechanism. Assume that and during the test mode. Changing the sign of will swap and [see (6)], and changing the sign of will change the function of DMSA1 to DMSA2 and vice versa [see (6) and (7)]. Let be a 2 s-complement number, then If ( ) is substituted for, then and (8) (9) Fig. 9. An M-testable 16-point FFT omega network. (10) It can be used to calculate. In the MSA module (see Fig. 3), the input sequence in normal mode. Suppose that in test mode and the array multiplier outputs are complemented, then the output value of the array multiplier becomes. We can modify the multiplier cells in the last column to realize the mechanism. Assume that a basic multiplier cell consists of two XOR, three AND, and one OR gates as depicted in Fig. 11(a). Fig. 11(b) shows a modified multiplier cell, where two XONR gates ( and ) replace the XOR gate. An extra input of (i.e., ) controls the circuit operation modes: for normal mode and for test mode, respectively. The two XNOR gates serve as an XOR gate and an XNOR gate in normal mode and test mode, respectively. The multiplier then produces negative output in test mode. This method relies on the implementation of the multiplier cell. Alternatively, we can add an XOR gate to each output of the array multiplier, and a controlling signal ( ) can be used to complement the output in test mode. Fig. 10. An M-testable 16-point FFT flip network. 16-point FFT omega and flip networks are shown in Figs. 9 and 10, respectively. Theorem 2: An -point FFT omega network based on DMSA1 (DMSA2) module is M-testable if the outputs of the DMSA1 (DMSA2) modules in are swapped, where and, and the function of the DMSA1 (DMSA2) module with ( ) is changed to that of DMSA2 (DMSA1), where. Theorem 3: An -point FFT flip network based on DMSA1 (DMSA2) module is M-testable if the outputs of each of the DMSA1 (DMSA2) modules in are swapped, where and, and the function of the DMSA1 (DMSA2) modules with ( ) is changed to that of DMSA2 (DMSA1), where. IV. C-DIAGNOSABLE FFT NETWORKS An FFT network is said to be C-diagnosable if there exists a diagnosis algorithm whose complexity (or number of test patterns to locate a faulty module) is independent of the network size. Many diagnosis (fault location) methods for the FFT networks have been proposed in the past, including online diagnosis schemes [10], [11], [14], [20] and offline ones [13], [15]. The complexity of these diagnosis methods depends on the size of the FFT networks, from to. We will propose a C-diagnosable design for the FFT networks in this section, i.e., the complexity is. Note that we will discuss the C-diagnosable scheme based on the M-testability conditions described in the previous section, though it also can be applied to other M-testability schemes proposed in [17], [18]. A. C-Diagnosability Conditions We will focus on the FFT butterfly network, though the discussion is applicable to other types of FFT network. The syndrome,,isa -bit vector defined

6 272 IEEE TRANSACTIONS ON VERY LARGE-SCALE INTEGRATION (VLSI) SYSTEMS, VOL. 10, NO. 3, JUNE 2002 Fig. 12. An eight-point FFT butterfly network. (a) A faulty module. (b) Two faulty modules. Fig. 11. (a) Multiplier cell. (b) Modified multiplier cell. for an -point FFT butterfly network, where the bit if and only if the th module at the last stage has incorrect output values. Exchanging the upper and lower outputs results in a dual syndrome. For example, if the fault is propagated from only the upper output of the faulty module in Fig. 12(a), then the syndrome is. Its dual syndrome can be obtained by exchanging the upper output to lower output. We have the following observations for the FFT butterfly network. 1),,, and form a four-point FFT block. 2) The fault propagation paths form a tree (see Lemmas 4 and 5 in the Appendix). An example is shown in Fig. 12(a), an eight-point FFT butterfly network with a faulty module, where the fault propagation tree is highlighted. 3) If, then for, where represents the outputs of the modified modules. 4) A fault propagated to both outputs of in a four-point FFT block will result in the same syndrome as when the fault is propagated to both outputs of in the FFT block. For example,,,, and form a four-point FFT block as shown in Fig. 12(b). A fault in or produces the same syndrome. 5) If a fault is propagated to only one output of a module, then the module is the fault site (according to Lemmas 4 and 5 in Appendix I-B). 6) The faulty module is in stage or, which can be determined by the number of 1s of the syndrome (see Lemma 6 in the Appendix). So far the fault can be located only to within two neighboring stages. Also, aliasing may result from different faulty modules in the same stage. The first problem can be solved by exchanging the outputs of the suspected faulty module in stage and comparing the syndromes. If the faulty module is in stage, then both its outputs are faulty. Note, that although there are possible faulty modules, we have only possible syndromes due to aliasing. If some modules from stage to stage can

7 LI AND WU: EFFICIENT FFT NETWORK TESTING AND DIAGNOSIS SCHEMES 273 Fig. 13. A four-point diagnosable FFT butterfly network. Fig. 14. The diagnosis algorithm DIA_ALG(). Fig. 15. Diagnosis example for Case 1. be switched to the blocking mode (explained below), then we can increase the number of possible syndromes to, i.e., the exact faulty module in stage can be located. If the faulty module is in stage, then we recover the exchanged outputs of to its original configuration. The faulty module in stage will propagate the fault to exactly one module in stage, so the same approach can be used to locate the fault in stage. We say an FFT network is diagnosable if the exact faulty module can be located. To make a network diagnosable, we can block the upper input of a module and replace it with the lower input (see the lower right module in Fig. 13) in order to avoid aliasing. For the example shown in Fig. 13, it is apparent that the syndromes for a faulty and faulty will be different. Therefore, the C-diagnosability conditions for the FFT butterfly, omega, and flip networks as stated in thms 4 6 (see Appendix I-B) can easily be proven. B. Diagnosis Algorithm Fig. 14 shows the diagnosis algorithm DIA_ALG() for the FFT networks. Once a fault is detected, the algorithm performs the diagnosis procedure by syndrome comparison as discussed above. The faulty module can be isolated to within two adjacent stages by counting the syndrome weight (see Lemma 6 in Appendix I-B). Note that the case when is trivial, and the faulty module (which is in the last stage) can be identified directly by the syndrome. If, then the blocking technique will be used, as shown in DIA_ALG(). A special case is, which indicates that the faulty module is in the first stage and both its outputs are faulty. Blocking is used directly. For other cases we need to obtain the new syndrome,, after output exchange. If, then the upper inputs of are blocked, where. The test pattern that de- tects the fault is applied again to locate the faulty module. If, the upper inputs of those specified modules also are blocked. However, to propagate the fault to the stage next to stage along a unique path, the exchanged outputs of,, must be recovered. The faulty module can then be identified by the syndrome after reapplying the test pattern. An eight-point FFT butterfly network will be used as an example to explain the diagnosis procedure for two different cases. Case 1: Assume that the output syndrome is after testing, i.e., the faulty module is in stage 0 or 1. The suspect modules are shown in Fig. 15(a), shaded. The outputs of the modules in stage 0 are then exchanged and the syndrome is either or, as shown in Fig. 15(b). If the syndrome is, then and are blocked, as shown in Fig. 16(a). The new syndrome will be or, indicating or is faulty, respectively. If, however, the syndrome after output exchange is, then and are blocked, and we recover the exchanged outputs of and to the original configuration as shown in Fig. 16(b). The faulty module can then be identified. Table I summarizes the four possible syndromes and the respective faulty modules. Case 2: If the output syndrome is after testing, then the faulty module must be in stage 0. All the modules in stage 0 are possible faulty modules as shown in Fig. 17(a). Therefore, only,,, and are blocked as shown in Fig. 17(b), and the faulty module can be identified. The possible syndromes and the respective faulty modules are shown in Table II. C. Design for C-Diagnosability To exchange the outputs, switches are added to the outputs of the modules from stages 0 to. It can easily be im-

8 274 IEEE TRANSACTIONS ON VERY LARGE-SCALE INTEGRATION (VLSI) SYSTEMS, VOL. 10, NO. 3, JUNE 2002 TABLE II POSSIBLE SYNDROMES AND RESPECTIVE FAULTY MODULES FOR CASE 2 Fig. 16. Diagnosis example for Case 1 (continued). TABLE I POSSIBLE SYNDROMES AND RESPECTIVE FAULTY MODULES FOR CASE 1 Fig. 18. A 3-bit MSA module with blockable q inputs. plemented by multiplexers. We now discuss the implementation of the blocking mechanism for DMSA1. It also is applicable to DMSA2. The upper input of DMSA1 is [see (6)]. Since is an operand of the binary adder (see Fig. 2) and each bit of is an input of the AND gate of the adder cell [see Fig. 4(c)], can be blocked by controlling the other input of the AND gate. A 3-bit MSA module with blockable inputs is shown in Fig. 18. In the shaded cell, the input originally connected to 1 is replaced by the control signal. V. ANALYSIS AND COMPARISON The hardware overhead is defined as the ratio of the additional transistors with respect to the total transistors of the original FFT network. The number of transistors of an MSA module is [18] (11) An -point FFT network has butterfly modules and each butterfly modules consists of four MSA modules. Therefore, the total number of transistors in an -point FFT network is (12) Fig. 17. Diagnosis example for Case 2. In Fig. 11, the modified cell has two additional transistors, since two XNOR gates can be implemented with eight transistors, while an XOR gate is implemented with six transistors [30]. The

9 LI AND WU: EFFICIENT FFT NETWORK TESTING AND DIAGNOSIS SCHEMES 275 Fig. 19. Hardware overhead with respect to n and N. number of modules whose function is exchanged is, each requiring extra transistors; and modules have swapped outputs in test mode, each requiring additional transistors. Each butterfly module also needs a switch ( transistors) to separate the butterfly module into two DMSA modules. Hence, the number of extra transistors of the M-testable design is Thus, the hardware overhead is (13) (14) It is about 0.17% for 16-bit numbers regardless of the FFT network size. The plots of with respect to and are depicted in Fig. 19. From the figure, we see that the hardware overhead is dependent on and is almost independent on. For the diagnosable design, only the output exchange mechanism needs extra hardware. The input blocking mechanism only requires a control signal. Each of the butterfly modules from stage 0 to requires switches to exchange the outputs. A switch can be implemented by four transistors, and there are outputs in each butterfly module. The number of additional transistors for the output exchange mechanism thus is Therefore, the hardware overhead is (15) (16) It is about 0.26% for 16-bit numbers and can be considered independent on when is large. We do not estimate the hardware overhead resulting from additional interconnects. It is difficult to estimate the area overhead without the layout information. However, since our design only needs to add local interconnects, except the control signals, area overhead due to additional interconnects will be small. The number of the inputs of a DMSA module is,soan -point FFT network can be pseudoexhaustively tested with patterns using the proposed M-testable design. The comparison results between ours and previous methods [13], [15], [17] are shown in Table III. In [17], an input-assignment technique was used to design M-testability FFT networks. Butterfly-level faults are considered and tests are needed. The required hardware overhead is very low since only a small amount of switches are required. In [13], testing and diagnosis approaches were proposed. An entire FFT network can be tested with operations proportional to (L-testability). In [15], a C-testability scheme was proposed. The number of tests is. They modified the binary adder and subtractor of the MSA module to a switchable adder/subtractor. The hardware overhead was not reported. As soon as an error is detected, our approach only needs two extra tests to identify the faulty module, i.e., fault location needs ( ) test patterns (independent of ). The FFT network, therefore, is C-diagnosable. In [15], the complexity of locating a faulty butterfly module is, and in [13] it is (with a limited functional fault model). The comparison is summarized in Table IV. Another advantage of the proposed M-testable design is that its built-in self-test (BIST) circuitry can be implemented easily. A binary counter which generates an exhaustive sequence for a single DMSA module can realize the test pattern generator. Since the network outputs are symmetric, they can be checked for possible faults by equality checkers [17]. The proposed C-diagnosable design also can be applied to previous testable FFT networks [15], [17], [18]. VI. CONCLUSION M-testability conditions for FFT butterfly, omega, and flip networks at the DMSA module level have been proposed. A novel design-for-testability technique based on the functional bijectivity property of the specified modules has been presented. It guarantees 100% fault coverage with negligible hardware overhead about 0.17% for FFT networks with 16-bit words. Our design also results in fewer test vectors compared with previous ones. A C-diagnosable technique for the FFT networks also has been proposed. By properly exchanging and blocking certain fault propagation paths, a faulty DMSA module can be located by a constant-time algorithm. The blocking mechanism can be implemented with negligible hardware overhead. Compared with previous methods, our method reduces the diagnosis complexity from to. For both testing and diagnosis, the hardware overhead for our scheme is only about 0.43% for 16-bit numbers regardless of the FFT network size.

10 276 IEEE TRANSACTIONS ON VERY LARGE-SCALE INTEGRATION (VLSI) SYSTEMS, VOL. 10, NO. 3, JUNE 2002 TABLE III COMPARISON WITH PREVIOUS TESTING APPROACHES TABLE IV COMPARISON WITH PREVIOUS DIAGNOSIS APPROACHES APPENDIX I LEMMAS AND THEOREMS A. Proof of M-Testability Theorems Lemma 1: The DMSA1 module has a bijective cell function if, i.e.,. Proof: Consider the input that maps to the output. By (6), for any input we obtain the output.if and, then. This holds only if since, which implies that, a contradiction to the assumption. Therefore, by definition the cell function is bijective. Lemma 2: The DMSA2 module has a bijective cell function if, i.e.,. Lemma 3: Consider an -point FFT network with twiddle factor, where. Wehave if and only if ; also, if and only if. Proof of Theorem 1: We first assume the network is based on the DMSA1 module. It is easy to see that an FFT butterfly network can be considered as being composed of four-point blocks. A four-point FFT block is shown in Fig. 20, where the outputs of the bottom-left DMSA1 module are swapped. Also, the function of the DMSA1 module is changed to that of DMSA2 if, so that according to Lemma 3. We apply a minimal complete sequence to every module in the first stage. The output sequence from every module is also minimal complete since the function of the module is bijective according to Lemma 1. Swapping the outputs of the bottom-left DMSA1 module (see Fig. 20) guarantees that every module in the second stage also receives a minimal complete input sequence. Fault effect propagation is automatic due to bijectivity. By definition, the four-point FFT butterfly network is M-testable. In an -point FFT butterfly network, the function of every DMSA1 module is bijective since the function of the DMSA1 modules with is changed to that of DMSA2 during the test mode. We label the stages of the -point butterfly network from 0 to, and the th module (counting from top to bottom) of the th stage as, where and. We also denote the outputs and of as and, respectively. The FFT butterfly network has the property that [, ] are the inputs of, and [, ] are the inputs of the. Furthermore,,,, and form a four-point FFT block. As discussed above, and receive minimal complete input sequences if and receive minimal complete input sequences, since the outputs of are swapped, i.e., each module in stage receives a minimal complete input sequence if each one in stage does. Again, fault effect propagation is automatic. By induction, the -point FFT butterfly network is M-testable. The M-testability of the network based on DMSA2 can be proved analogously, by Lemmas 3 and 2. Proof of Theorem 2: The goal is to guarantee that the input of every DMSA1 module of an -point FFT omega network receives a minimal complete sequence. In the omega network, (, ) are the inputs of, and (, ) are the inputs of, i.e.,,,, and form a four-point FFT block. Therefore, and receive minimal complete input sequences if and receive minimal complete input sequences, since the outputs of are swapped. We conclude that each module in stage receives a minimal complete input sequence if each one in stage does. By induction, the -point omega network is M-testable. The M-testability of the network based on DMSA2 can be proved by Lemmas 3 and 2 in a similar way. Proof of Theorem 3: In the FFT flip network (, ) are the inputs of, and (, ) are the inputs of,so,,, and form a four-point FFT block. Therefore, and receive minimal input sequences if and receive minimal input sequences, since the outputs of the module are swapped. We conclude that each module in stage receives a minimal complete input sequence if each one in stage does. By induction, the -point FFT flip network is M-testable. The M-testability of the network based on DMSA2 can be proved in a similar way. B. C-Diagnosability Lemmas and Theorems Lemmas 4 and 5 can be proven easily by (6) and (7). Lemma 4: A fault on any input of a DMSA1 module will be automatically propagated to both outputs of the module if,or. Lemma 5: A fault on any input of a DMSA2 module will be automatically propagated to both outputs of the module if,or.

11 LI AND WU: EFFICIENT FFT NETWORK TESTING AND DIAGNOSIS SCHEMES 277 Fig. 20. A four-point FFT butterfly network. Lemma 6: In a faulty -point FFT network, the faulty module is in stage or if the weight (i.e., number of 1s) of the syndrome is, where. Proof: If stage has a faulty module, then the weight of the syndrome must be one. If stage has a faulty module, then the weight of the syndrome may be one or two, depending on whether the fault is propagated to one or two outputs of the faulty module. Similarly, if a faulty module is in stage, then the weight of the syndrome may be two or four. The lemma is thus true by induction. Theorem 4: An -point FFT butterfly network with a faulty module in stage is diagnosable if both outputs of that module are faulty, and the upper inputs of are blocked, where,,, and. Theorem 5: An -point FFT omega network with a faulty module in stage is diagnosable if both outputs of that module are faulty, and the upper inputs of are blocked, where,,, and. Theorem 6: An -point FFT flip network with a faulty module in stage is diagnosable if both outputs of that module are faulty, and the upper inputs of are blocked, where,,, and. REFERENCES [1] A. V. Oppenheim and R. W. Schafer, Discrete-Time Signal Processing. Englewood Cliffs, NJ: Prentice-Hall, [2] A. E. Cetin, O. N. Gerek, and Y. Yardimci, Equiripple FIR filter design by FFT algorithm, IEEE Signal Processing Mag., vol. 14, pp , Mar [3] P. Noll, MPEG digital audio coding, IEEE Signal Processing Mag., vol. 14, pp , Sept [4] J. O Brien, J. Mather, and B. Holl, A 200 MIPS single-chip 1K FFT processor, in Proc. IEEE Int. Solid-State Circuit Conf. (ISSCC), Feb. 1989, pp , 327. [5] E. Bidet, D. Castelain, C. Joanblanq, and P. Senn, A fast single-chip implementation of 8192 complex point FFT, IEEE J. Solid-State Circuits, vol. 30, pp , Mar [6] C. C. W. Hui, T. J. Ding, J. V. McCanny, and R. F. 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Comput., vol. 22, pp , Dec [27] C.-W. Wu and S.-K. Lu, Designing self-testable cellular arrays, in Proc. IEEE Int. Conf. Comput. Design (ICCD), Cambridge, MA, Oct. 1991, pp [28] P. R. Menon and A. D. Friedman, Fault detection in iterative arrays, IEEE Trans. Comput., vol. 20, pp , May [29] S.-K. Lu, J.-C. Wang, and C.-W. Wu, C-testable design techniques for iterative logic arrays, IEEE Trans. VLSI Syst., vol. 3, pp , Mar [30] N. Weste and K. Eshraghian, Principles of CMOS VLSI Design: A Systems Perspective, 2nd ed. Reading, MA: Addison-Wesley, Jin-Fu Li received the B.S. degree from the National Taiwan University of Science and Technology, Taipei, Taiwan, and the M.S. degree in electrical engineering from National Tsing Hua University, Hsinchu, Taiwan, in 1995 and 1999, respectively. He is currently working toward the Ph.D. degree at the National Tsing Hua University. His research interests include advanced VLSI design and testing, system-on-a-chip testing, fault-tolerant design, embedded memory testing, diagnosis, and self repair.

12 278 IEEE TRANSACTIONS ON VERY LARGE-SCALE INTEGRATION (VLSI) SYSTEMS, VOL. 10, NO. 3, JUNE 2002 Cheng-Wen Wu (S 86 M 87 SM 95) received the B.S.E.E. degree from National Taiwan University, Taipei, Taiwan, and the M.S. and Ph.D. degrees, in electrical and computer engineering from the University of California, Santa Barbara (UCSB) in 1981, 1985, and 1987, respectively. From 1981 to 1983, he was an Ensign Instructor at the Chinese Naval Petty Officers School of Communications and Electronics, Tsoying, Taiwan. From 1983 to 1984, he was with the Information Processing Center of the Bureau of Environmental Protection, Executive Yuan, Taipei, Taiwan. From 1985 to 1987, he was a Post-Graduate Researcher at the Center for Computational Sciences and Engineering at UCSB. Since 1988, he has been with the Department of Electrical Engineering, National Tsing Hua University (NTHU), Hsinchu, Taiwan, where he is currently a Professor. From 1996 to 1998, he served as the Director of NTHU s Computer and Communications Center, and from 1998 to 1999, as the Director of the Technology Service Center. From August 1999 to February 2000, he was a Visiting Faculty Member of the Electrical and Computer Engineering Department, UCSB. Since August 2000, he has been the Chair of the Electrical Engineering Department of NTHU. He is also the Director of the IC Design Technology Center, NTHU. His research interests include design and testing of high performance VLSI circuits and systems. Dr. Wu was the Technical Program Chair of the IEEE 5th Asian Test Symposium (ATS), 1996, and the General Chair of ATS, He is an Associate Editor for the Journal of the Chinese Institute of Electrical Engineers (JCIEE) and a Guest Editor of the JCIEE Special Issue on Design and Test of System-on-Chip (SoC), he was a Guest Editor of the Journal of Information Science and Engineering (JISE), and the Special Issue on VLSI Testing. He received the Distinguished Teaching Award from NTHU in 1996, the Outstanding Electrical Engineering Professor Award from the Chinese Institute of Electrical Engineers (CIEE) in 1997, and the Distinguished Research Award from National Science Council in 2001.