COMPUTER ENGINEERING PROGRAM

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Griffin Williams
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1 Learning Objectives COMPUTER ENGINEERING PROGRAM California Polytechnic State University CPE 169 Experiment 9 A Digital Alarm System 1. Finite State Machine (FSM) To understand how VHDL behavioral modeling is used to implement a FSM that controls a relatively complex digital system 2. Digital Systems Design To understand the interaction between various modules in a digital system To design and implement a system-level digital circuit based on a given specification 3. Xilinx Design Methodology and VHDL To gain more experience with VHDL structural modeling Introduction and Overview This experiment introduces a common sequential circuit in the context of digital system design: the Finite State Machine (FSM). Two common uses of the FSM are in the design of counters and system controllers. This experiment uses a FSM to control the various operating characteristics of the digital alarm system that was discussed in the previous experiments. The stated digital alarm system contains four main functional modules; three of these modules have been designed in previous experiments. The fourth module is the FSM and is the main focus of this experiment. The various modules of the digital alarm system are integrated using VHDL structural modeling thus highlighting the code reuse approach to digital design. Finite State Machine Design Using VHDL Implementing FSMs in VHDL is straight-forward using VHDL behavioral modeling. As you have probably noticed by now, any time that you are able to implement a circuit by describing its behavior (as opposed to describing the actually logic used to implement the behavior), you ll be allowing the VHDL synthesis process to do most of the grunt-work that has traditionally been required of the circuit designer. Once you understand these techniques, you ll be able to quickly apply them to the implementation step of any FSM problem. This approach is so straight-forward that it can be considered a template approach to implementing FSMs. But before we start on this, let s make note of a few things: The VHDL behavioral approach to FSM design reduces the many opportunities for errors associated with other techniques. The behavioral approach allows to you go from the state transition diagram to VHDL code: no equation generation is necessary. What enables this approach to become a cookie-cutter method for future FSM designs is to thoroughly understand each part of the template. The good news is that there are not that many parts to understand. Moreover, the effort you put into understanding these parts is an investment in understanding both VHDL and sequential circuit design in general. The Low-Carb VHDL tutorial contains a more complete version of the description that follows. If the description that follows seems inadequate, you may need to peruse the VHDL tutorial. 3/7/

2 FSMs Using VHDL Behavioral Modeling A block diagram for a generic FSM is shown in Figure 1. This diagram looks fairly generic but some important descriptive names are used for several of the blocks in the design. The next state decoder is a block of combinatorial logic that uses the current external inputs and the current state of the FSM to decide upon the appropriate next state for the FSM. In other words, the inputs to this block are decoded to produce an output that represents the next state of the FSM. The next state becomes the present state of the FSM when the clock input to the state registers block becomes active. The state registers block contains storage elements that store the present state of the machine. The inputs to the output decoder are decoded via combinatorial logic to generate the desired external outputs. The FSM diagram in Figure 1 is a generic model because the outputs can be considered either Mealy or Moore-types. Recall that Mealy outputs are a function of both the present state of the FSM and at least one external input while Moore outputs are only a function of the present state. Figure 1: Block diagram for a generic FSM. The FSM model shown in Figure 1 is probably the model that was used to introduce you to the concept of FSMs. But this is not how we ll model FSMs in the context of VHDL. The true power of VHDL emerges in its dealings with FSMs and behavioral modeling. As you ll see, the versatility of VHDL behavioral modeling removes the need for large paper designs of endless K-maps and gate-level combinatorial logic. The approach we ll describe in this section is modeled by the block diagram shown in Figure 2. Although it does not look that much clearer, you ll soon find the FSM model shown in Figure 2 to be a straight-forward method to implement FSMs. The behavioral model divides the FSM into two VHDL processes. One process, the Synchronous Process, handles all the matters regarding clocking and other controls associated with the storage element. The other process, the Combinatorial Process, handles all the matters associated with the Next State Decoder and the Output Decoder of Figure 1. Note that the Output and Next State decoder blocks in Figure 1 are generally comprised solely of combinatorial logic. There is some new lingo used in the description of signals seen in Figure 2. The inputs labeled Parallel Inputs are used to signify inputs that act in parallel to each of the storage elements. These inputs would include enables, presets, clears, etc. The inputs labeled State Transition Inputs include external inputs that control state transitions (determining the next states for the FSM). These inputs also include external inputs used to decode Mealy-type outputs. Figure 2: Model for VHDL implementations of FSMs. 3/7/

3 The approach that follows is referred to as the dependent PS/NS style for implementing FSMs. The best way to describe this approach is through an example problem. Although the following example is not the simplest FSM that was ever conceived, it does have all the required elements for a demonstration of this implementation method. EXAMPLE Write VHDL code that implements the FSM modeled by the state diagram below. Use a Dependent PS/NS coding style in your implementation. Consider the state variables to be external outputs of the FSM. Figure 3: An example of a VHDL FSM behavioral description. Figure 4: Black Box diagram for the FSM of the example. Figure 4 shows the black box diagram for the solution of the example while Figure 5 provides a VHDL solution to the example problem. A few of the more interesting points regarding the solution are listed below. A VHDL type is declared to represent the states in this FSM. This is an example of an enumeration type in VHDL. There is an internal numerical representation for each of the listed state type variables, but we only need to deal with their textual representation. The synchronous process is equal in form and function to a D flip-flop implementation. The only difference is we ve substituted PS and NS for D and Q, respectively. Note that in the synchronous process, there is no else statement, which is how VHDL infers the storage elements. Even though the code looks somewhat complicated, if you examine it closely, you can see that everything is nicely compartmentalized in the solution. There are two processes. The synchronous process handles the asynchronous reset and the assignment of a new state upon the arrival of the system clock. The combinatorial process handles the tasks not contained in the synchronous process: the determination of outputs, and the generation of the next state of the FSM. Because the two processes operate concurrently (remember, VHDL processes are concurrent statements), they can be considered as working in a lock-step manner. Changes to signal NS that are generated in the combinatorial process forces an evaluation of the synchronous process. When signal changes are actuated by the synchronous process on the next clock edge, the changes in the PS signal causes the combinatorial process to be evaluated. 3/7/

4 The case statement in the combinatorial process provides a when clause for each state of the FSM as well as a catch-all when others case. The Moore output is a function of only the present state. This is expressed by the fact that the assignment of the Z1 output is unconditionally evaluated in each when clause of the case statement in the combinatorial process. The Mealy-type output and the next-state assignment are handled inside the conditional statement (if) in the individual clauses of the case statement. This is because both the Z2 output and the next state assignment are functions of the external input X. Figure 5: The annotated solution the example problem. 3/7/

5 Figure 6: A digital alarm system for the Nexys board. Procedure Procedure Overview: In this experiment, you ll be designing and/or assembling the various components of a digital alarm system. All but one of the components in the digital alarm system were designed and tested in previous experiments. 1) Design a FSM that acts as a controller for the digital alarm system. 2) Design and test the digital alarm system. Procedure 1: Digital Alarm System FSM 1. Design a Finite State Machine for the Alarm System based on the following design criteria. The block diagram of the FSM is shown in Figure 7. Figure 7: Black-box diagram of the digital alarm FSM. 3/7/

6 a. This FSM has three inputs (SYS_ON_L, BREAK_IN, and CLK) and two outputs (ALARM and SYS_ARMED. NOTE: The SYS_ON_L signal is active low. This means that when the signal is in the 0 state, the signal is active. In terms of the circuit shown in Figure 7, when this signal is active, or asserted, the alarm system is turned on. When the signal is not asserted, the system is turned off (unarmed). Active low signals are typically noted with the _L suffix appended onto the signal name. b. The FSM has three states: UNARMED, ARMED, and ALARM_SOUNDING. c. When the FSM is in the UNARMED state, the system is off. If the SYS_ON_L input is asserted while in this state, the FSM transitions to the ARMED state on the next active clock edge. All other input combinations keep the system in the UNARMED state. Keep in mind that turning off the alarm is only accomplished by entering the correct alarm access code. If the correct access code is not entered on the switches, the system will "ARM" itself. d. When the FSM is in the ARMED state, the system is on and ready to detect break-ins. If the SYS_ON_L input is not asserted, the system is turned off by going back into the UNARMED state. If the SYS_ON_L is asserted and the BREAK_IN input is also asserted, the FSM transitions to the ALARM_SOUNDING state. Any other input combinations keep the system in the ARMED state. The SYS_ARMED output is only asserted while in the ARMED state. e. When the FSM is in the ALARM_SOUNDING state, a break-in has been detected. If the SYS_ON_L input is unasserted, the system is turned off and the FSM transitions to the UNARMED state. The FSM remains in the ALARM state for all other possible inputs conditions. The ALARM output is asserted while in the ALARM_SOUNDING state, and unasserted at all other times. 2. Draw a state transition diagram depicting the behavior of the FSM alarm system control. Also provide the corresponding PS/NS table. Include both items with your lab report. 3. Using the FSM behavioral modeling described at the beginning of this experiment, enter your design in VHDL using the Xilinx ISE software. Define a state_type which has the following states: ALARM_SOUNDING, ARMED, and UNARMED. 4. Simulate your design using ModelSim and provide an output of this simulation with your lab report. Be sure to include some pertinent annotations on your simulation. Procedure 2: Digital Alarm System 1. Reusing the modules you have designed and implemented in previous experiments, implement the Digital Alarm System shown in Figure 6. In the same project that you created for your FSM, add the VHDL modules to the project for your BCD-to-7-segment Display Decoder, Priority Encoder, and 4-bit Comparator. NOTE: The Priority Encoder was designed in Experiment 6. Recall that the 3-bit output of the priority encoder is the binary representation of the highest numbered input that is asserted. The STROBE output on the priority encoder is asserted when one or more inputs are asserted. NOTE: The BCD-to-7-segment display decoder was also designed in Experiment 6. 3/7/

7 NOTE: The comparator was designed in Experiment 7. In this current experiment, one of the 4-bit inputs to the comparator is used to hardwire a 4-bit access code into the hardware. The other input (4-bits) to the comparator is connected to switches and used to arm and disarm the digital alarm system. 2. Use VHDL structural modeling to assemble the four components of the digital alarm system as shown in Figure 6. Create a new "top-level" VHDL module that declares, instantiates, and interconnects the various design modules. a. Use buttons for the inputs to the Priority Encoder. The button inputs behave as break-in sensors in your alarm system. b. Use the four right-most switches to input the access codes to one set of inputs on the 4-bit comparator. These allow you to enter a 4-bit number that generates an EQ signal (to turn the alarm system OFF) if it matches the hardwired preset code. c. Connect the outputs of the FSM to two LEDs (LD5 & LD4 on the Nexys board). Include all VHDL source code files for the Digital Alarm System with your lab report as well as a complete block diagram. 3. Demonstrate your working Digital Alarm System to your instructor. Do not reveal your hardwired alarm code; your instructor will have to break the code in order to turn off your alarm system. Questions 1. Was your FSM designed as a Mealy or Moore-type machine? Would it matter which type of FSM was used for this design? Fully explain your answer. 2. How many flip-flops were required for the Digital Alarm System? 3. Using the PS/NS table that describes the FSM in this procedure, determine the Boolean logic equations for generating the excitation inputs of the required flip-flops from the input signals and the assigned State Variables of your FSM. (Assume that D flip-flops are used for the FSM.) 4. Explain how the priority encoder will respond if multiple sensors detect a break-in at the same time. 5. In Experiment 8, you designed a 4-bit binary counter. How could you, or more precisely your instructor, use the counter to crack your Digital Alarm System access code? Could the same code cracking approach be used if the alarm access code was 32 bits in length instead of 4? 6. Discuss how the system clock frequency affects the general operation of the digital alarm system. Are there any potential problems that could arise if the system clock is too fast, or too slow? 7. If a break-in is in-progress when the Digital Alarm System is being armed (break in occurs while initially in the UNARMED state), what is the longest possible time (t max ) before the alarm will sound after the access code switches are changed to arm the system? Assume that the system clock frequency was 10 Hz. Under the same circumstances, what is the shortest possible time (t min ) before the alarm will sound? Fully justify your answers (in words), and draw a Timing Diagram to illustrate the operation of the Alarm System for the situations leading to the longest and shortest response times. Include both input signals (BREAK_IN and SYS_ON_L), the system clock CLK, and both output signals (ARMED and ALARM) in your diagram. Show the t max and t min times on your diagram. 3/7/

8 8. If the system clock frequency was 10 Hz, what is the maximum time someone could break-in (activating one of the sensors) without being detected. Fully support your answer and assume the alarm system is already armed for this problem. 9. What would happen if the alarm system was armed, and a break-in was detected at the same instant that the system was being disarmed by a correct Access Code entry (both the Sys_On_L and Break_In signals switch at the same time)? Fully explain your answer keeping in mind that the correct response is dependent on your particular implementation of the alarm system s FSM. 3/7/

Reconfigurable Computing Lab 02: Seven-Segment Display and Digital Alarm Clock

Reconfigurable Computing Lab 02: Seven-Segment Display and Digital Alarm Clock Informatik Cauerstr. 98 Erlangen Reconfigurable Computing Lab : Seven-Segment Display and Digital Alarm Clock Problem (Seven-segment display) A seven-segment display consists of seven light emitting diodes