Reconfigurable Computing Lab 02: Seven-Segment Display and Digital Alarm Clock

Transcription

1 Informatik Cauerstr. 98 Erlangen Reconfigurable Computing Lab : Seven-Segment Display and Digital Alarm Clock Problem (Seven-segment display) A seven-segment display consists of seven light emitting diodes (LEDs), which can be turned ON or OFF independently. As shown in Figure, to display a digit between and 9, it is necessary to switch ON and OFF different segments. Figure : Different number representations on a seven-segment display A logic to control a seven-segment display has to be specified in VHDL. This logic has to turn ON segments considering that they are active low. That means, turns a segment ON and a turns it OFF. <= Number <= 9 SSG_ SSG_ SSG_ SSG_ SSG_ SSG_ SSG_ Figure : Block diagram of a controller for a seven-segment display Preparation Complete the following VHDL code for a seven-segment decoder:

2 LIBRARY IEEE; USE IEEE.STD_LOGIC_.ALL; USE IEEE.STD_LOGIC_ARITH.ALL; USE IEEE.STD_LOGIC_UNSIGNED.ALL; ENTITY sevensegment IS PORT (NUMBER : IN INTEGER RANGE TO 9; DIGIT : OUT STD_LOGIC_VECTOR ( downto )); END sevensegment; ARCHITECTURE behavioral OF sevensegment IS SIGNAL DIGIT_in : STD_LOGIC_VECTOR ( DOWNTO ); BEGIN PROCESS(NUMBER) BEGIN CASE NUMBER is -- WHEN => DIGIT_in <= ""; WHEN OTHERS => DIGIT_in <= ""; END CASE; END PROCESS; DIGIT <=...; END behavioral; Complete the waveform in Figure. Number Digit[:] Digit[] Digit[] Digit[] Digit[] Digit[] Digit[] Digit[] Figure : Waveform of the signals to the seven-segment display

3 Steps:. Complete the file sevensegment.vhd. Test the functionality by simulating the design with Questa Sim Using a terminal, change from your home directory to /scratch-local/rc/lab Load Questa Sim with the command line: module load modelsim/.c_x8_-pc-linux Start Questa Sim: vsim& Create a new project: File -> New -> Project. Then, Project name: lab and Project location: /scratch-local/rc/lab/ Add the following files to your project: sevensegment.vhd and tb_sevensegment.vhd. Compile all files by selecting the options Compile Order and Auto Generate For starting the simulation, select: Simulate -> Start Simulation. Hence, select the file tb_sevensegment as shown in Fig. Using the VSIM terminal, execute the command lines: do load_waveforms and run -all. Stop the simulation and observe the waveforms from the tab wave. For a better visualization, you can select simulation -> Runtime Options and change the default radix to unsigned. Figure : Start Simulation tab of Questa Sim Problem (Designing a digital alarm clock) A controller for the alarm clock shown in Figure shall be developed. Specification of the alarm clock Inputs Switch S (BTN) to display and set the current time

4 S Hours Minutes S ALM Time On/Off S Timeset Alarm S S Figure : Alarm Clock Switch S (BTN) to display and set the alarm time Switch S (BTN) to increment hours Switch S (BTN) to increment minutes Switch S (SW7) to activate the alarm Switch S (SW) to reset the board Outputs Four seven-segment displays are used to show the current time or the alarm time One LED shows if the alarm is activated States The controller has three different states as shown in Figure : time: This is the default state. Here, the current time is displayed and if the alarm is equal to the current time, the LED (LD7) is switched ON. set time: This state is reached when S is pressed. Here, if S and S are pressed simultaneously, the hours are incremented. Similarly, if S and S are pressed together, the minutes are incremented. By releasing S, the controller returns to state time. set alarm: This state is reached when S is pressed. If S and S are pressed at the same time, the hours are incremented. However, if S and S are pressed, the minutes are incremented. By releasing S, the controller returns to state time.

5 else S = S = else set_time time set_alarm else S = S = Figure : State diagram of the digital alarm clock Architecture The alarm clock has to be implemented on the Digilent Spartan- Starter Kit board (see Figure 7). The board contains a Spartan- FPGA (Field Programmable Gate Array). The board is also S S S S S S Figure 7: Digilent Spartan- Starter Kit board [] equipped with four seven-segment displays, four push-buttons, eight switches, eight LEDs, one parallel port, one serial port, one PS interface, and one VGA interface. To implement our alarm clock, the seven-segment displays, the four push buttons, (BTN, BTN, BTN, BTN) and two switches (SW, SW7) will be used. A LED (LD7) will be used as an alarm. We set the following mapping: S BTN, S BTN, S BTN, S BTN, S SW7, S SW, which is used as reset button. The structure of the VHDL design is given in Figure 8. Here are the files for designing the alarm clock: sevensegment.vhd controls one seven segment display and was created in the first part of the lab. Display.vhd presents a number between and on two displays.

6 LED 7 reset S S S S S FSM Display Display Display Display MUX And Alarm Controller Seven- Segment SSG SSG SSG SSG controller Alarm alarm_clock clk Figure 8: Block diagram of the alarm clock Display.vhd shows a number between and 9 on other two displays. controller.vhd defines a finite state machine for the alarm clock and sets the display variables. MUX and alarm.vhd multiplexes the displays and sets the alarm. alarm clock.vhd is the top hierarchy of the design. alarm clock.ucf is the user constraint file, which defines how inputs and outputs ports of the design are connected to physical pins of the FPGA. Steps Complete the files alarm_clock.vhd and controller.vhd. Simulate the entire design with ModelSim by using tb alarm clock.vhd. Then, use the Xilinx ISE for synthesizing the design and programming the board, as follows:. using a terminal, load the tool ISE: module load ise/._x8_-pc-linux. Start ISE by executing the following command line: ise&. Create a new project for Spartan, device: XCS, package: FT, and speed: -. Add all VHDL and UCF files from /scratch-local/rc/lab/. Note, the testbench files tb_alarm_clock.vhd and tb_sevensegment.vhd are used only for simulation, thus, they cannot be used for synthesis.. Generate the bitstream and use the tool impact to program the board.

7 References [] Digilent Inc. Spartan- Starter Board. Available at: 7