An FPGA Spectrum Sensing Accelerator for Cognitive Radio

Transcription

1 An FPGA Spectrum Sensing Accelerator for Cognitive Radio George Eichinger Miriam Leeser Kaushik Chowdhury NEWSDR October 2011 This work is sponsored by the Department of the Air Force under Air Force Contract FA C The opinions, interpretations, conclusions, and recommendations are those of the authors and are not necessarily endorsed by the United States Government GE100111U-100A.ai

2 Cognitive Radio Overview Spectrum Holes Frequency Time Cognitive radios allow you to operate in unused portions of spectrum GE092111U-101A

3 Cognitive Cycle Transmitted Signal Radio Environment Stimuli Spectrum Characterization Spectrum Mobility Primary User Detection Spectrum Sensing Decision Request Spectrum Hole Spectrum Sharing Spectrum Decision GE092111U-602AA.ai

4 Cognitive Cycle Transmitted Signal Radio Environment Stimuli Spectrum Characterization Spectrum Mobility Primary User Detection Spectrum Sensing Decision Request Spectrum Hole Focus of This Talk Spectrum Sharing Spectrum Decision GE092111U-602AA.ai

5 Outline Cognitive Radio overview Project motivation and goals Hardware platform Spectrum sensing algorithm Results of implementation Summary GE092111U-102A

6 Motivation Existing Software Defined Radio (SDR) systems take too long to perform spectrum sensing Software spectrum sensing involves transmitting data to and from the host computer which adds latency and processing time Moving spectrum sensing closer to the receiver reduces latency and makes real time spectrum sensing feasible t s T Sensing Cycle: Ts = t s + T GE092111U-103A

7 Project Goals Create platform for hardware level Cognitive Radio (CR) research Perform spectrum sensing as close to the receiver and as fast as possible Report results to host indicating whether or not a channel is free Design system with reconfigurable, parameterized hardware and programmable software GE092111U-104A

8 Outline Cognitive Radio overview Project motivation and goals Hardware platform Cognitive Radio Universal Software Hardware (CRUSH) Spectrum sensing algorithm Results of implementation Summary GE092111U-102A

9 Introducing CRUSH Cognitive Radio Universal Software Hardware (CRUSH) Xilinx FPGA Board Ettus N210 Custom Interface Board Standard software defined radio and FPGA development board Custom interface board to connect the two boards GE092111U-105A.ai

10 Ettus Research N210 GE092111U-106A Agile front end Low cost Xilinx Spartan 3A DSP FPGA for RX/TX Minor changes for CRUSH

11 Xilinx FPGA Development Board Specifications: Xilinx V6-LX240t FPGA 1* high pin count FMC 1* low pin count FMC 1* PCI express MB DDR3 RAM Benefits: Standard FPGA development board Ability to communicate at full ADC and DAC rate with the Versatile external IO/memory Increases from FPGA: 6.6 more RAM, 4.5 more LUTs, 2.5 faster GE100111U-107A

12 Custom Interface Board 2 Mictor connectors Allows for to communicate with two s via the 34 pin parallel debug port 2 minisas posts Transmit serial data with up to two s via MIMO port 2 spare Mictor connectors Spare FPGA IO FMC HPC/LPC interface Fully compatible with the Can be used with and LPC interface like the SP605 with just one Only custom part of CRUSH Allows full 100 MSPS IQ bidirectional datalink up to 800 MB/s GE100111U-108A

13 Outline Cognitive Radio overview Project motivation and goals Hardware platform Spectrum sensing algorithm Results of implementation Summary GE092111U-102A

14 Spectrum Sensing Algorithm Receive Data Perform FFT Apply Threshold Report Data Amplitude Amplitude (db) Amplitude (db) Boolean Time Frequency Frequency Frequency GE092111U-109A

15 System Diagram Spectrum Sensing without CRUSH Digital Down (DDC) Digital Up (DUC) Frequency Selection ADC Radio DAC Data Transmitter Receiver FFT All processing occurs on the host No real-time guarantee GE092111U-110AA

16 System Diagram Spectrum Sensing with CRUSH Digital Down (DDC) Digital Up (DUC) Frequency Selection ADC Radio DAC Data Transmitter Receiver FFT ADC Data FO Samples FFT Freq Bins Threshold Detector Freq Bins Frequency Status Accumulator GE092111U-110AA

17 Advantages of CRUSH Ability to process received data in real time FPGA: Parallel clock driven data bus : Serial packetized data Higher throughput datalink FPGA: 100 MHz 32 bit DDR interface (800 MB/s) : Gigabit Ethernet (125 MB/s) Less processing load on the host More time for high level policy/protocol execution Reconfigurable hardware allows for parameters such as FFT size to be changed in real time New protocols with functionality partly residing on host and partly on the radio are now possible GE092111U-111A

18 Outline Cognitive Radio overview Project motivation and goals Hardware platform Spectrum sensing algorithm Results of implementation Summary GE092111U-102A

19 Test Setup Functional Verification Signal Generators GE092111U-112A

20 Results Functionality Verification Lab measurement with one tone at 31 MHz and a center frequency of 25 MHz point FFT Processed by FPGA X: 3.086e+007 Y: FFT of data Processed in Matlab 0 X: 3.1e+007 Y: 0 Amplitude (dbc) Amplitude (dbc) Frequency in MHz Frequency in MHz GE092111U-113A

21 Test Setup Runtime Analysis Digital Down (DDC) Digital Up (DUC) Frequency Selection ADC ADC Data Two Way Status Radio DAC Data Transmitter Receiver FFT Two Way Status FO Samples FFT Timers GE092111U-114A

22 Test Setup Runtime Analysis Digital Down (DDC) ADC ADC Data Two Way Status Digital Up (DUC) Frequency Selection Radio DAC Data Transmitter Receiver FFT Two Way Status 1. -> FPGA (start test) 2. FPGA (reset timers) 3. FPGA -> (start test) 4. -> /FPGA (test pattern) 5. FPGA FFT Done (stops timer) 6. -> FPGA (FFT Done) 7. FFT Done (stops timer) FO Samples FFT Timers GE092111U-115AA

23 Test Setup Runtime Analysis Digital Down (DDC) ADC ADC Data Two Way Status Digital Up (DUC) Frequency Selection Radio DAC Data Transmitter Receiver FFT Two Way Status 1. -> FPGA (start test) 2. FPGA (reset timers) 3. FPGA -> (start test) 4. -> /FPGA (test pattern) 5. FPGA FFT Done (stops timer) 6. -> FPGA (FFT Done) 7. FFT Done (stops timer) FO Samples FFT Timers GE092111U-115AA

24 Test Setup Runtime Analysis Digital Down (DDC) ADC ADC Data Two Way Status Digital Up (DUC) Frequency Selection Radio DAC Data Transmitter Receiver FFT Two Way Status 1. -> FPGA (start test) 2. FPGA (reset timers) 3. FPGA -> (start test) 4. -> /FPGA (test pattern) 5. FPGA FFT Done (stops timer) 6. -> FPGA (FFT Done) 7. FFT Done (stops timer) FO Samples FFT Timers GE092111U-115AA

25 Test Setup Runtime Analysis Digital Down (DDC) ADC ADC Data Two Way Status Digital Up (DUC) Frequency Selection Radio DAC Data Transmitter Receiver FFT Two Way Status 1. -> FPGA (start test) 2. FPGA (reset timers) 3. FPGA -> (start test) 4. -> /FPGA (test pattern) 5. FPGA FFT Done (stops timer) 6. -> FPGA (FFT Done) 7. FFT Done (stops timer) FO Samples FFT Timers GE092111U-115AA

26 Test Setup Runtime Analysis Digital Down (DDC) ADC ADC Data Two Way Status Digital Up (DUC) Frequency Selection Radio DAC Data Transmitter Receiver FFT Two Way Status 1. -> FPGA (start test) 2. FPGA (reset timers) 3. FPGA -> (start test) 4. -> /FPGA (test pattern) 5. FPGA FFT Done (stops timer) 6. -> FPGA (FFT Done) 7. FFT Done (stops timer) FO Samples FFT Timers GE092111U-115AA

27 Test Setup Runtime Analysis Digital Down (DDC) ADC ADC Data Two Way Status Digital Up (DUC) Frequency Selection Radio DAC Data Transmitter Receiver FFT Two Way Status 1. -> FPGA (start test) 2. FPGA (reset timers) 3. FPGA -> (start test) 4. -> /FPGA (test pattern) 5. FPGA FFT Done (stops timer) 6. -> FPGA (FFT Done) 7. FFT Done (stops timer) FO Samples FFT Timers GE092111U-115AA

28 Test Setup Runtime Analysis Digital Down (DDC) ADC ADC Data Two Way Status Digital Up (DUC) Frequency Selection Radio DAC Data Transmitter Receiver FFT Two Way Status 1. -> FPGA (start test) 2. FPGA (reset timers) 3. FPGA -> (start test) 4. -> /FPGA (test pattern) 5. FPGA FFT Done (stops timer) 6. -> FPGA (FFT Done) 7. FFT Done (stops timer) FO Samples FFT Timers GE092111U-115AA

29 256-point FPGA FFT Timing Analysis 270 ns 2560 ns 9410 ns Action Clocks Time (µs) Incremental (µs) Start Test Data enters FPGA Clock Domain FFT Starts All Data inside FPGA FFT Complete Total GE092111U-116A

30 Results Runtime Analysis FFT Size FPGA Average (µs) Average (µs) Speed-up ( ) Speed-up between 8 and 774 FPGA timing scales log linear with FFT size timing driven by packet transmit time and internal buffering GE092111U-117AA

31 Results Runtime Analysis FFT Size FPGA Average (µs) Average (µs) Speed-up ( ) Speed-up between 8 and 774 FPGA timing scales log linear with FFT size timing driven by packet transmit time and internal buffering GE092111U-117AA

32 Conclusion Created CRUSH platform Combined powerful FPGA with versatile front end Produced custom interface board to allow high speed data transfer Moved processing closer to receiver Implemented spectrum sensing on CRUSH Achieved more than 100 performance for FFT sizes of interest Reduced load on host computer Fully configurable GE092111U-118A

33 Future Work Integrate the spectrum sensing module into research on Cognitve Radio at Northeastern University Explore other methods of performing hardware accelerated spectrum sensing such as wavelet analysis Utilize the CRUSH platform to migrate additional software radio functions into reconfigurable hardware Perform non-radio research with the CRUSH platform utilizing its front end and FPGA back end GE092111U-119A

34 Questions? Miriam Leeser Kaushik Chowdhury George Eichinger GE092111U-120A

35 Issues Using the N210 FPGA N210 has a Xilinx Spartan 3A-DSP3400A Timing closure is an issue 100 MHz clock speed makes timing closure more difficult Long build time and complex existing firmware Spartan 3A DSP line is two generations behind the latest Xilinx products N210 FPGA is an improvement over the FPGA used in the 2 but still not enough 64 k Xilinx FFT takes 367 RAM36 blocks, more than the entire N210 FPGA No ability for partial reconfiguration applications Limited external IO and memory GE100111U-121A