Programming the Cell BE

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1 Programming the Cell BE Max Schneider Chair of Computer Science 3 - Computer Architecture Friedrich-Alexander-University Erlangen-Nuremberg October 26, 2010 Max Schneider (FAU) PParRA October 26, / 46

2 Aim of this course get to know the Cell BE Architecture get the ability to use the number-crunching SPEs get the ability to use DMA-Transfers get understanding of SIMD concepts introducing some common loop optimizations Max Schneider (FAU) PParRA October 26, / 46

3 The Cell BE Concept (1) fully compliant with the 64 bit PowerPC Architecture single-chip multiprocessor with nine processor elements operating in a shared, coherent memory heterogeneity allows detachment of control-intensive from compute-intesive tasks significant improvement in peak computational performance and chip-area-and-power efficiency over conventional PC processors using SIMD concepts in all processor elements overlapping of computational tasks and data transfers Max Schneider (FAU) PParRA October 26, / 46

4 The Cell BE Concept - Levels of parallelism in the CBEA SIMD parallelization Superscalar parallelization Multiple execution units Multiple CBEA processors Max Schneider (FAU) PParRA October 26, / 46

5 The Cell BE Architecture Max Schneider (FAU) PParRA October 26, / 46

6 The Synergistic Processing Element (SPE) Max Schneider (FAU) PParRA October 26, / 46

7 SPEs in numbers 256 KB local store 128-entry, 128 bit wide register file 128 bit SIMD architecture 16 Byte / cycle load-store bandwidth, quadword aligned data only (25.6 GB/s) 128 Byte / cycle DMA-transfer bandwidth (25.6 GB/s) EIB bandwidth GB/s 128 Byte instruction prefetch per cycle Max Schneider (FAU) PParRA October 26, / 46

8 Single precision peak performance PowerXCell 8i 3.2 GHz clock rate on SPE 4-way SIMD (float) Fused Multiply and Add (FMA): 2 operations in one 1 FMA / cycle adds to (Operations) 1 = 25.6 GFLOP/s 8 SPEs on a chip: = GFLOP/s PowerPC has also 4-way FMA: GFLOP/s Max Schneider (FAU) PParRA October 26, / 46

9 Double precision peak performance PowerXCell 8i 3.2 GHz clock rate on SPE 2-way SIMD (double) Fused Multiply and Add (FMA) 1 FMA / cycle adds to (Operations) 1 = 12.8 GFLOP/s 8 SPEs on a chip: = GFLOP/s PowerPC doesn t support 2-way SIMD Max Schneider (FAU) PParRA October 26, / 46

10 Using one SPE - Basics PPE uses SPE contexts to control SPE program execution SPE contexts are associated with the physical SPEs by OS SPE threads are independent from other threads running at the same time libspe2 library included in IBM Cell SDK contains SPE management functionality, needed by the PPE Max Schneider (FAU) PParRA October 26, / 46

11 Using one SPE - Step by step Create a context for each SPE Load the SPE program in those contexts Start context execution Destroy all contexts Max Schneider (FAU) PParRA October 26, / 46

12 Using one SPE - Step by step (visualized) Max Schneider (FAU) PParRA October 26, / 46

13 Using one SPE - Creation of contexts spe context create - Create a new SPE context parameters: flags - a bit-wise OR of modifiers that are applied when the SPE context is created gang - associate the new SPE context with this gang context Max Schneider (FAU) PParRA October 26, / 46

14 Using one SPE - Load the SPE program in a SPE context spe program load - Load an SPE main program parameters: spe - A valid pointer to the SPE context for which an SPE program should be loaded program - A valid address of a mapped SPE program Max Schneider (FAU) PParRA October 26, / 46

15 Using one SPE - Start context execution spe context run - Request execution of an SPE context parameters: spe - A pointer to the SPE context that should be run entry - The entry point at which the SPE program should start executing runflags - A bit mask that can be used to request certain specific behavior for the execution of the SPE context argp - An (optional) pointer to application specific data, and is passed as the second parameter to the SPE program envp - An (optional) pointer to environment specific data, and is passed as the third parameter to the SPE program stopinfo - An (optional) pointer to a structure which is filled with all information available about the reason why the SPE program stopped running Max Schneider (FAU) PParRA October 26, / 46

16 Using one SPE - Destroy the SPE context spe context destroy - Destroy the specified SPE context spe - A pointer to the SPE context that should be destroyed Max Schneider (FAU) PParRA October 26, / 46

17 Using one SPE - Hello World Max Schneider (FAU) PParRA October 26, / 46

18 Using multiple SPEs Max Schneider (FAU) PParRA October 26, / 46

19 Using multiple SPE - Hello World Max Schneider (FAU) PParRA October 26, / 46

20 Build Process Max Schneider (FAU) PParRA October 26, / 46

21 Build Process (visualized) Max Schneider (FAU) PParRA October 26, / 46

22 Data transfers using DMA - Basics Used for data transfers between main memory and local stores of SPEs Transfers are carried out by SPEs MFC asynchronously to computations in SPUs Used to hide transfer latency by preloading data used in future computations MFC supports out-of-order execution of DMA-transfers 32-bit Tag-Ids are assigned to DMA-transfers allowing status control of those transfers Data in LS is referenced using Local Store Addresses (LSA) Data in main memory is referenced using effective address (EA) Max Schneider (FAU) PParRA October 26, / 46

23 Data transfers using DMA - Characteristics Naturally aligned transfer sizes: 1, 2, 4, 8 or multiples of 16-Bytes Maximum transfer size: 16 KB Peak performance if both the EA and LSA are 128 Byte aligned and transfer size is multiple of 128 Bytes Two separate and independent DMA-request queues: MFC SPU Command Queue: used by associated SPU (up to 16 requests) MFC Proxy Command Queue: used by PPE and other SPEs or extern devices (up to 8 requests) List transfers for transfers bigger than 16 KB Each DMA transfer specified in the list transfers up to 16 KB Up to 2048 list elements Supports scatter-gather functionality A DMA transfer, no matter the size, is always transferred in segments of 128 Bytes Max Schneider (FAU) PParRA October 26, / 46

24 Data transfers using DMA - Make transfers Max Schneider (FAU) PParRA October 26, / 46

25 Data transfers using DMA - Example (PPE) Max Schneider (FAU) PParRA October 26, / 46

26 Data transfers using DMA - Example (SPE) Max Schneider (FAU) PParRA October 26, / 46

27 SIMD - Basics (1) Single Instruction Multiple Data Applies one instruction to multiple data at once (add,sub,multiply,shift,...) 128-bit wide Registers divided into several logical items Max Schneider (FAU) PParRA October 26, / 46

28 SIMD - Basics (2) SIMD instruction sets in PPE (VMX) and in SPEs (SPU ISA) Vector type variables are 16 Byte aligned 16 Byte aligned scalar arrays can be casted to vector arrays and back Max Schneider (FAU) PParRA October 26, / 46

29 SIMD - Example (Addition of two vectors) Max Schneider (FAU) PParRA October 26, / 46

30 SIMD - Loop SIMD zation Max Schneider (FAU) PParRA October 26, / 46

31 SIMD - Shuffle c = spu shuffle(a,b,pattern) Shuffles vectors a and b by selecting bytes and storing in c Each byte in pattern selects a byte in vector a or b (or one of three constants) Bytes in vector a are numbered 0x00 to 0x0F Bytes in vector b are numbered 0x10 to 0x1F Max Schneider (FAU) PParRA October 26, / 46

32 SIMD - Shuffle usage example 4 x 4 matrix transpose accomplishable using only 8 shuffle operations Max Schneider (FAU) PParRA October 26, / 46

33 SIMD - Select Bit c = spu sel(a,b,pattern) For each bit in vector pattern, corresponding bit from either vector a or vector b is selected If a pattern bit is 0, corresponding bit from vector a is selected If a pattern bit is 1, corresponding bit from vector b is selected Max Schneider (FAU) PParRA October 26, / 46

34 SIMD - Select bit usage example Removing branches by executing both branch alternatives After branch condition is evaluated, the correct results are selected Max Schneider (FAU) PParRA October 26, / 46

35 Common Loop Optimizations Max Schneider (FAU) PParRA October 26, / 46

36 Common Loop Optimizations - Loop Unroll Max Schneider (FAU) PParRA October 26, / 46

37 Common Loop Optimizations - Code vectorization Max Schneider (FAU) PParRA October 26, / 46

38 Common Loop Optimizations - Explicit Load and Store Operation vc[i] = va[i] * vb[i] + vc[i] is broken down to load va[i] load vb[i] load vc[i] compute va[i] * vb[i] + vc[i] store vc[i] Making that explicit in the SPE code vai = va[i]; // load va[i] vbi = vb[i]; // load vb[i] vci = vc[i]; // load vc[i] vci = vai * vbi + vci; // compute vc[i] = vci; // store vc[i] Max Schneider (FAU) PParRA October 26, / 46

39 Common Loop Optimizations - Explicit Load and Store Max Schneider (FAU) PParRA October 26, / 46

40 Common Loop Optimizations - Software Pipelining A pipeline has S stages and executes S different instructions concurrently, by executing a different piece of each every cycle Doing the same in the loop is called Software Pipelining Max Schneider (FAU) PParRA October 26, / 46

41 Common Loop Optimizations - Software Pipelining Max Schneider (FAU) PParRA October 26, / 46

42 Common Loop Optimizations - Software Pipelining Max Schneider (FAU) PParRA October 26, / 46

43 Common Loop Optimizations - Again Loop Unroll Max Schneider (FAU) PParRA October 26, / 46

44 Common Loop Optimizations - Again Software Pipelining Max Schneider (FAU) PParRA October 26, / 46

45 Common Loop Optimizations - What is the peak performance for this loop 2 * N floating point operations 3 loads and 1 store for 4 scalar elements packed in one SIMD-vector (4 * N / 4 mem. ops) SPE issues 1 mem. operation per cycle: N cycles 3.2 GHz clock on SPE: 2 * N (FLOPs) * 3.2 / N (mem. cycles) = 6.4 GFLOP/s Version 6: 4.46 GFLOP/s (69.69% of peak performance) Max Schneider (FAU) PParRA October 26, / 46

46 Your Tasks Implement a simple matrix multiplication algorithm on the CELL BE Matrix A,B,C C=A B (+C) C[x,y]= P Col 1 k=0 A[x,k] B[k,y]+C[x,y] Use DMA-Transfers to get matrix elements to the SPEs Use SIMD-Instructions for all calculations Implement the 2D-Jacobi-Thermodiffusion on the CELL BE Optional Use main memory for all synchronization steps Use 1-8 SPEs and measure algorithm runtimes Is there a noticeable performance downgrade effect, when multiple SPEs are used Implement double-buffering technics to overlap data transfer with computations on SPEs Apply learned loop optimization technics to get better performance Max Schneider (FAU) PParRA October 26, / 46

The Cell Processor Computing of Tomorrow or Yesterday?

The Cell Processor Computing of Tomorrow or Yesterday? Computing of Tomorrow or Yesterday? Torsten Höfler Department of Computer Science TU Chemnitz 28th February 2006 Outline 1 The Vision 2 3 4 Cell Applications Conclusion The Researchers started in mid 2000