CXI Detector Status, Cost & Schedule

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1 Status, Cost & Schedule LCLS Detector Physicist June 3,

2 Outline Technical Scope Basic detector module (Cornell) Detector assembly Data acquisition Major Interfaces Design Reviews Cost & Schedule 2

3 Team Gruner Group at Cornell University - Biophysics, Soft Condensed Matter, and X-ray Detector Development Lab Sol Gruner; project leader Hugh Philipp, Mark Tate, Marianne Hromalik, Lucas Koerner SLAC PPA Electrical & Software Engineering - Gunther Haller, Ryan Herbst, Amedeo Perazzo, Chris O Grady, Matt Weaver, Dieter Freytag SLAC PPA Mechanical Engineering - Martin Nordby, Matthew Swift LUSI CXI team - Sebastien Boutet - CXI Instrument Scientist - Paul Montanez - CXI Lead Engineer 3

4 LDAC LCLS Detector Advisory Committee: Gareth Derbyshire (chair): Rutherford Appleton Laboratory, UK Erik Heijne (interim chair): CERN, Switzerland Eric Eikenberry: PSI, Switzerland Heinz Graafsma: DESY / XFEL, Germany Ronnie Shepherd: LLNL, USA Lothar Struder: MPI / Semiconductor Laboratory, Germany Albert Walenta: University of Siegen, Germany Yoshiyuki Amemiya: University of Tokyo, Japan Track technical progress, check if detector specs meet the original requirements and involved in technology choices Other topics e.g. DAQ and system integration LDAC report 4

5 CXI Requirements The Coherent X-ray Imaging instrument will image nanoscale objects, including single or small clusters of bio-molecules The detector needs to image the 2D diffraction pattern with a large area detector with minimum dead area With the intense (10 12 ph) and short (100 fs) LCLS pulses at 120 Hz one needs integrating detectors with fast readout (< 8 ms) CXI spec. Readout noise Full well capacity Pixel size < 0.3 ph ph 110 μm Number of pixels 750 ( ). Energy 4-8 kev 5

6 LCLS beam Detector in vacuum 10-7 Torr Resolution depends on the sample-detector distance Requires translation stage 600 mm Remote Aperture resizing 1-10 mm Cooling C ~110 microns 6

7 Test results Low gain: Full Well ~ > kev x-rays 7

8 Characterization of Detector 8 kev x-rays, 75 micron pinhole. Niels 12van Bakel

9 CXI Assembly Simulations changed design Packaging Bump & wire bonding Assembly tools Alignment & position stability Interface to DAQ 1.1 Gbps per quadrant Cold strap Quadrant raft 2x2 detector package (4 per quadrant) Digital board 2x1 Analog board 9

10 Front View 1 mm Aperture 10

11 Front View 6 mm Aperture 11

12 Front View 9.4 mm Aperture 12

13 CXI 2x1 Module Packaging Front End Board One board per detector Part of detector assembly ASIC s on back side of detector Pixel array detector Carrier board Flex cable bent back out of the way 2x1 Detector Assembly Jig Diode-ASIC assembly bonded to carrier board 2x1 assembly held for wire bonding and testing 13

14 LDAC Recommendations Increase interaction with user community Close interaction with Instrument Scientists Team leader meetings & Instrument workshops Cornell progress Focus on full array with 16 ASICs Since prototype detector functions according to specs Foresee adequate cooling for stable operation Need a 2x1 module operational in May 2009 Progress towards a first tested module appears to be relatively slow The 2x1 modules to be delivered to SLAC after full testing at Cornell. It is recommended to discuss this in detail, so that resources can be found, if needed Assemble only known good die (KGD) The basic components for a full system are available Recommended that the desirable redesign of the CMOS chip is discussed in the framework of a future, follow-up project, so that priority can be given to the schedule of delivery of detector modules this Fall

15 Cornell Schedule 15

16 Cornell Plan Technical Addendum-D (5/1/08-4/30/09, $1,235k): Measurement of the existing prototypes with x-rays Identification of areas for improvement Identification of areas that need to be developed for full-array implementation Design and redesign of circuitry as driven by steps 2 and 3. Simulation of circuits to be included in next submission Low-level physical layout of circuits Verification of layout Submission of design to MOSIS, including second full-lot submission. Design and fabrication of test electronics for a particular submission Needs extension Work with the SLAC science team to define geometrical format and packaging of detector 16

17 Cornell Plan Technical Addendum-D (5/1/08-4/30/09, $1,235k): Test and calibrate final detector; develop calibration procedures. Design and fabricate hybrid compatible with the packaging scheme Write test reports and documentation Design & fabricate 2nd large detector diode; development of 2x1 module Design high speed data transfer and storage for final detector compatible with LCLS DAQ Bump bond final detector diodes and ASICs Prepare report/ conduct review Perform radiation tests Assembly of final detector; work with SLAC on shielding and EMI Test vacuum compatibility of detector module Needs extension 17

18 CXI vs. Cornell milestones CXI Schedule (WBS 1.3): CXI FDR Cornell Detector packaging in Feb CXI RCV: Cornell detector from LCLS in April (needs update) CXI AVAIL: Ready for installation, CXI detector stage in Oct CXI COMP: CXI Early Science Components Installation in May Conservative, driven by KB mirrors CXI COMP: CXI Final Installation Complete in November Cornell Schedule: XE254_2160 2D detector received at SLAC in November 2009 Cornell 2D PAD detector installed February 2010 optimistically CXI ready in December 2010 Early installation in hutch 3 in September

19 Detector - DAQ Interface L1: Acquisition Beam Line Data Detector + ASIC FEE Timing L0: Control L2: Processing L3: Data Cache Detector - Experiment Specific Front-End Electronics - Local configuration registers and state machines, FPGA used to transmit to DAQ system Timing info from the accelerator timing system, distributed to the detectors and L1 boards L0 Control: operate DAQ, control a run & configure the detector, telemetry monitoring Beam Line Data is beam quality information, used to veto events L1 DAQ: Acquire FEE data, detector calibration, event building (beam line data), image processing, veto, 10 Gb/s ethernet 19

20 Detector DAQ Each quadrant connects to external interface board via LVDS signals 125Mhz Clock Reset (Optional) Command 2 Data Output Lines Interface board interfaces to RCE via 2 PGP links Data Rates 1 ASIC = 16 bits * 185 rows * 194 cols * 120Hz = 68.9Mbs 1 Quadrant = 16 ASICS * 68.9Mbps = 1.1Gbps 1 Chamber = 1.1Gbps * 4 = 4.4Gbps 20

21 Register Command Data Interface Detector specific blocks PCDS blocks RegAddr[23:0] RegDataOut[31:0] RegReq RegOp ReqAck RegFail Register Block MGT Transceiver Fiber Transceiver MGT L1 Node RegDataIn[31:0] Interface defined between FEE and L1 CmdCtxOut[23:0] CmdOpcode[6 :0] CmdEn Command Block PGP Block - Common interface among different experiments FrameTxEnable FrameTxSof FrameTxDataWidth FrameTxEof FrameTxEofe FrameTxData[15:0] FEE FPGA Data Block - Provide data, command and register interfaces - Custom point-to-point protocol (Pretty Good Protocol, PGP) implemented as FPGA IP core - FEE FPGA assumed to be Xilinx family with ( MGT ) Multi Gigabit Transceivers 21

22 Mechanical Interface Mechanical interface Detector stability Thermal & Cooling interface Vacuum requirements Electrical interface Power requirements Controls interface 22

23 Detector Testing at SLAC SLAC Front End Development board, Digital & Analog PCB for CXI Additional testing; feedback to Detector Groups Improves integration into LCLS & LUSI instruments SLAC custom made DAQ board (L1) available for detector groups Start testing at SLAC Bench tests SSRL beam tests Detector test lab; x-ray tube 23

24 Summary & Outlook Technical progress Schedule updated to meet CXI ready for early scientific experiments: phase I Nov 09 phase II Feb 10 CXI Installation at SLAC Complete Dec 10 CXI Early Science... 24

25 Summary & Outlook Technical progress Schedule updated to meet CXI ready for early scientific experiments: phase I Nov 09 phase II Feb 10 CXI Installation at SLAC Complete Dec 10 CXI Early Science... 24

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