Reduced Memory and Low Power Architectures for CORDIC-based FFT Processors

Transcription

1 J Sign Pocess Syst (0) 66:9 DOI 0.007/s x Reduced Memoy and Low Powe Achitectues fo CORDIC-based FFT Pocessos Edal Ouklu & Xin Xiao & Jafa Saniie Received: 0 August 00 /Revised: Mach 0 /Accepted: 5 Mach 0 /Published online: 6 Apil 0 # Spinge Science+Business Media, LLC 0 Abstact This pape pesents a pipelined, educed memoy and low powe CORDIC-based achitectue fo fast Fouie tansfom implementation. The poposed algoithm utilizes a new addessing scheme and the associated angle geneato logic in ode to emove any ROM usage fo stoing twiddle factos. As a case study, the adix- and adix- FFT algoithms have been implemented on FPGA hadwae. The synthesis esults match the theoetical analysis and it can be obseved that moe than 0% eduction can be achieved in total memoy logic. In addition, the dynamic powe consumption can be educed by as much as 5% by educing memoy accesses. Keywods FFT. CORDIC. VLSI. Low powe Intoduction E. Ouklu (*) : X. Xiao : J. Saniie Depatment of Electical and Compute Engineeing, Illinois Institute of Technology, 0 South Deabon Steet, Chicago, IL 6066, USA edal@ece.iit.edu Discete Fouie Tansfom (DFT) is one of the coe opeations in digital signal pocessing and communication systems. Many fundamental algoithms can be ealized by DFT, such as convolution, spectum estimation, and coelation. Futhemoe, DFT is widely used in standad embedded system applications such as wieless communication potocols equiing Othogonal Fequency Division Multiplexing [], and ada image pocessing using Synthetic Apetue Rada [] and Softwae Defined Radio []. Howeve, DFT is difficult to implement diectly due to its computational complexity. In pactice, Fast Fouie tansfom (FFT) is used fo educing the complexity of computations. Fo FFT pocessos, buttefly opeation is the most computationally demanding stage. Taditionally, a buttefly unit is composed of complex addes and multiplies, and the multiplie is usually the speed bottleneck in the pipeline of the FFT pocesso. The Coodinate Rotation Digital Compute (CORDIC) [] algoithm is an altenative method to ealize the buttefly opeation without using any dedicated multiplie hadwae. CORDIC algoithm is vesatile and hadwae efficient since it equies only add and shift opeations, making it suitable fo the buttefly opeations in FFT [5]. Instead of stoing actual twiddle factos in a ROM, the CORDIC-based FFT pocesso needs to stoe only the twiddle facto angles in a ROM fo the buttefly opeation. In ecent yeas, seveal CORDIC-based FFT designs have been poposed fo diffeent applications [6 9]. In [6], non-ecusive CORDIC-based FFT was poposed by eplacing the twiddle factos in FFT achitectue by noniteative CORDIC mico-otations. It educes the ROM size; howeve, it does not eliminate it completely. Lin [7] poposed a mixed-scaling-otation CORDIC algoithm to educe the total iteations, but it inceases the hadwae complexity. Jiang [8] intoduced Distibuted Aithmetic to the CORDIC-based FFT algoithms, but the DA look-up tables ae costly in implementation. Gaido [9] poposed a memoyless CORDIC algoithm to educe the memoy equiements fo a CORDIC-based FFT pocesso, but implementation is complex. Conventionally, a CORDIC-based FFT pocesso needs a dedicated memoy bank to stoe the necessay twiddle facto angles fo the otation. In this study, we popose a modified CORDIC algoithm fo FFT pocessos which eliminates the need fo stoing the twiddle facto angles.

2 0 J Sign Pocess Syst (0) 66:9 The algoithm geneates the angles successively by an accumulato. With this appoach, memoy equiements of an FFT pocesso can be educed by moe than 0%. Memoy eduction impoves with the inceased adix size. Futhemoe, the angle geneation cicuit consumes less powe consumption than angle memoy accesses. Hence, the dynamic powe consumption of the FFT pocesso can be educed by as much as 5%. Since the citical path is not modified with the CORDIC angle calculation, system thoughput does not change. The oganization of the pape is as follows: In Section, CORDIC algoithm fundamentals and the design of CORDIC-based FFT pocesso ae descibed. The poposed memoy-efficient algoithm and it s hadwae achitectue ae pesented in Section fo adix- FFT whee is a powe of. Hadwae synthesis esults ae discussed in Section. FFT and CORDIC Algoithm case, a special data addessing scheme is equied to pevent the data conflict. In [0], a new addess scheme has been poposed to ealize this function and it can be extended to any adix FFT. This special addessing scheme is adopted fo CORDIC based FFT implementation []. CORDIC algoithm was poposed by J.E. Volde []. It is an iteative algoithm to calculate the otation of a vecto by using only additions and shifts. Figue shows an example fo otation of a vecto V i. It can be shown that otation can be simplified to: x iþ ¼ x i y i d i i y iþ ¼ y i þ x i d i i ðþ ð5þ Hee, the diection of each otation is defined by d i and the sequence of all d i s detemines the final vecto. d i is given as: ( ) ifz i < 0 d i ¼ ð6þ þifzi 0 The -point discete Fouie tansfom is defined by X ðkþ ¼ X n¼0 whee W nk xðnþw nk nk k ¼ 0; ; :::; ;W ¼ e jp nk ðþ ¼ e jp nk is the so-called twiddle facto. Fo -point FFT, thee ae log stages and each stage contains / buttefly opeations. The following equations descibe the adix- buttefly opeation at stage m. x mþ ðpþ ¼x m ðpþþx m ðqþ ðþ φ 0 x mþ ðqþ ¼½x m ðpþ x m ðqþšw ðþ φ Each buttefly opeation needs fou data accesses (two ead and two wite). Two two-pot memoy banks can povide fou data access in each clock cycle, but in this y V ( xi+, y ) i+ i+ V i ( i i x, y ) φ n 0 φ α x Figue Rotate vecto V i ðx i ; y i Þ to V iþ ðx iþ ; y iþ Þ. Figue Poposed stuctue of a pipelined CORDIC unit.

3 J Sign Pocess Syst (0) 66:9 Table Addess geneation table of the poposed design fo 6-point adix- FFT. Buttefly counte B (bbb0) Stage 0 Stage Stage Stage addess bbb0 facto angle addess b0bb facto angle addess bb0b facto angle addess bbb0 facto angle p p p p p p p p p p p p 6p p p 6p p whee z i is called angle accumulato and given by z iþ ¼ðz i d i actan i Þ ð7þ All opeations descibed though Eqs. 7 can be ealized by only additions and shifts; theefoe, CORDIC algoithm does not equie dedicated multiplies. CORDIC algoithm is often ealized by pipeline stuctues, leading to high pocessing speed. Figue shows the basic stuctue of the pipelined CORDIC unit. As shown in Eq., the key opeation of FFT is xðnþw nk nk,(w ¼ e jp nk ). This is equivalent to Rotate x (n) by angle p nk opeation which can be ealized easily by the CORDIC algoithm. Without any complex multiplications, CORDIC-based buttefly can be fast. An FFT pocesso needs to stoe the twiddle factos in memoy. CORDIC-based FFT doesn t have twiddle factos but needs a memoy bank to stoe the otation angles. Fo adix-, -point, m-bit FFT, m bits memoy needed to stoe angles. In the next section, a new CORDIC FFT design is pesented using a single accumulato which geneates all the necessay angles instantly. Poposed Codic-based FFT In the past, seveal multi-bank addessing schemes have been used to ealize paallel and pipelined FFT pocessing [], but those methods ae not suitable fo the poposed memoy educed, CORDIC-based FFT. In these schemes, the twiddle facto angles ae not in egula inceasing ode and this esults in a moe complex design fo angle geneatos []. As shown in Table, using a new addessing scheme fist poposed in [0], the twiddle facto angles follow a egula, inceasing ode, which can be geneated by a simple accumulato. Table shows the addess geneation table of the poposed design fo 6-point adix- FFT. It can be seen that twiddle facto angles ae sequentially inceasing, and evey angle is a multiple of the basic angle p, which is p 8 fo 6-point FFT. Fo diffeent FFT stages, the angles incease always one step pe clock cycle. Hence, an angle geneato cicuit composed of an accumulato, and an output latch can ealize this function, as shown in Figue. Contol signal fo the latch that enables o disables the accumulato output is simple and it is based on the cuent FFT buttefly stage and addess bits b b b 0 (see Table ). Figue shows the basic stuctue of poposed design fo adix- FFT pocessing. Fou egistes and eight -to- multiplexes ae used. Registes ae needed befoe and afte the buttefly unit to buffe the intemediate data in ode to goup two sequential buttefly opeations togethe. This way, the conflict-fee in-place data accessing can be ealized. This egiste-buffe design can be extended to any adix FFTs. Figue Angle geneato fo the poposed design. π

4 J Sign Pocess Syst (0) 66:9 Figue Memoy educed adix- CORDIC FFT pocesso. Fo adix-, the stuctue can be simplified by using just fou egistes, but fo adix- FFT, egistes ae needed. Figue 5 shows the basic stuctue of fo adix- FFT. Geneally, fo an = n -point FFT, the addessing and contol logic ae mainly composed of seveal components: An (n )-bit buttefly counteb ¼ b n b n...b b 0 will povide the addess sequences and the contol logic of the angle geneato. In stage p, the memoy addess is given by b p b p...b b 0 b n b n...b p, which is otate ight p bits of buttefly counte B. Meanwhile, the contol logic of the latch of the angle geneato is detemined by the sequence of the patten; b n b n...b p (p 0 s). Fo adix-, = n -point, m-bit FFT, (each data is m-bit complex numbe; m-bit each fo the eal pat and imaginay pat) by using the angle geneato, 5m bits memoy equied by the conventional CORDIC can be educed to m which coesponds to 0% eduction. Fo highe adix FFT, the eduction is even moe significant. Fo adix- FFT, the saving is ð Þm bits out of ð Þm, which conveges to.% eduction. Results and Conclusion The poposed designs fo both adix- and adix- FFT algoithms have been ealized by Veilog-HDL and implemented on an FPGA chip (STRATIX-III EPSE50C). Synthesis esults shown in Table confim that the poposed design can educe memoy usage fo FFT pocessos without any tangible incease in the numbe of logic elements used when compaed against the conventional CORDIC imple- In Out R R R R R R In Out R R In Out R R Figue 5 Memoy educed adix- CORDIC-based FFT.

5 J Sign Pocess Syst (0) 66:9 Table FPGA implementation esults fo adix- and adix- FFT. Radix- Radix- Poposed CORDIC FFT Design Conventional CORDIC FFT Poposed CORDIC FFT Design Conventional CORDIC FFT 56-point FFT Total logic elements,7 (9-bit accumulato),86 5,89 (0-bit accumulato) 5,76 Total memoy bits 8,67 0,70 8,78,800 Dynamic Powe 6.87 mw 56. mw 7.5 mw mw 0-point FFT Total logic elements,77 (-bit accumulato),78 5,99 (-bit accumulato) 5,797 Total memoy bits,8,0,0 5,59 Dynamic Powe 5.07 mw mw 9.0 mw 96.6 mw 096-point FFT Total logic elements,809 (-bit accumulato),757 5,99 (-bit accumulato) 5,86 Total memoy bits,55 6,0,608 80,760 Dynamic Powe.78 mw.85 mw 50. mw 57.7 mw mentation (i.e., angles ae stoed in memoy). Futhemoe, dynamic powe consumption is educed (up to 5%) with no delay penalties. The implementation esults ae in accodance with the theoetical analysis. Refeences Confeence on Electo/Infomation Technology, EIT 009, 7 0, June.. Xiao, X., Ouklu, E., & Saniie, J. (00) Reduced Memoy Achitectue fo CORDIC-based FFT. In IEEE Intenational Symposium on Cicuits and Systems, Ma, Y. (999). An effective memoy addessing scheme fo FFT pocessos. IEEE Tansactions on Signal Pocessing, 7(), Wey, C., Lin, S., & Tang, W. (007). Efficient memoy-based FFT pocessos fo OFDM applications. In IEEE Intenational Conf. on Electo-Infomation Technology, May.. Fanucci, L., Foliti, M., & Gonchi, F. (999). Single-chip mixedadix FFT pocesso fo eal-time on-boad SAR pocessing. In 6th IEEE Intenational Confeence on Electonics, Cicuits and Systems,, Mittal, S., Khan, M., & Sinivas, M. B. (007). On the suitability of Buun s FFT algoithm fo softwae defined adio. In 007 IEEE Sanoff Symposium, (pp. 5), Ap.. Volde, J. (959). The CORDIC tigonometic computing technique. IEEE Tansactions on Electonic Computes, 8(8), Despain, A. M. (97). Fouie tansfom computes using CORDIC iteations. IEEE Tansactions on Electonic Computes, (0), Abdullah, S. S., am, H., McDemot, M., & Abaham, J. A. (009). A high thoughput FFT pocesso with no multiplies. In IEEE Intenational Conf. on Compute Design, pp Lin, C., & Wu, A. (005). Mixed-scaling-otation CORDIC (MSR- CORDIC) algoithm and achitectue fo high-pefomance vecto otational DSP applications. IEEE Tansactions on Cicuits and Systems I, 5(), Jiang, R. M. (007). An aea-efficient FFT achitectue fo OFDM digital video boadcasting. IEEE Tansactions on Consume Electonics, 5(), Gaido, M., & Gajal, J. (007). Efficient memoy-less CORDIC fo FFT Computation. In IEEE Intenational Confeence on Acoustics, Speech and Signal Pocessing,, 6), Ap. 0. Xiao, X., Ouklu, E., & Saniie, J. (009). Fast memoy addessing scheme fo adix- FFT implementation. In IEEE Intenational Edal Ouklu eceived the B.S. degee in electonics and communication engineeing fom Technical Univesity of Istanbul, Istanbul, Tukey, in 995, the M.S. degee in electical engineeing fom Bogazici Univesity, Istanbul, in 999, and the Ph.D. degee in compute engineeing fom Illinois Institute of Technology, Chicago, in 005. He is cuently an Assistant Pofesso with the Depatment of Electical and Compute Engineeing, Illinois Institute of Technology, whee he is also the Diecto of VLSI and SoC Reseach Laboatoy. His eseach inteests ae econfiguable computing, advanced signal pocessing achitectues, hadwae/softwae codesign, and embedded systems fo sensos.

6 J Sign Pocess Syst (0) 66:9 Xin Xiao eceived the Ph.D. in electical engineeing fom Illinois Institute of Technology, Chicago, IL, in 00. He is cuently a senio membe of technical staff with ZTE US Laboatoy in J. His eseach inteests ae in digital cicuit and system design, signal pocessing with FPGA/ASIC, and system design in optical signal pocessing. Jafa Saniie eceived the B.S. degee in electical engineeing fom the Univesity of Mayland, College Pak, in 97, the M.S. degee in biomedical engineeing fom Case Westen Reseve Univesity, Cleveland, OH, in 977, and the Ph.D. degee in electical engineeing fom Pudue Univesity, West Lafayette, I, in 98. Since 98, he has been with the Depatment of Electical and Compute Engineeing, Illinois Institute of Technology, Chicago, whee he is a Filme Pofesso, Associate Chai and Diecto of the Embedded Computing and Signal Pocessing Reseach Laboatoy. His eseach inteests and activities ae in embedded digital systems, digital-signal pocessing with field-pogammable gate aays, and ultasonic signal and image pocessing.