CDB4352. Evaluation Board for CS4352 CS4352. Description. Features. Demonstrates Recommended Layout And Grounding Arrangements

Transcription

1 CD4352 Evaluation oa fo CS4352 Featues Desciption Demonstates Recommene Layout n Gouning angements CS8416 Receives S/PDIF, & EIJ-340- Compatible Digital uio Heaes fo Extenal PCM uio Requies Only a Digital Signal Souce an Powe Supplies fo a Complete Digital-to- nalog Convete System The CD4352 evaluation boa is an excellent means fo quickly evaluating the CS bit, high-pefomance steeo D/ convete. Evaluation equies an analog signal analyze, a igital signal souce, an a powe supply. nalog line-level outputs ae povie via RC phono jacks. The CS8416 igital auio eceive IC povies the system timing necessay to opeate the Digital-to-nalog convete an will accept S/PDIF an EIJ-340-compatible auio ata. The evaluation boa may also be configue to accept extenal timing an ata signals fo opeation in a use application uing system evelopment. ORDERING INFORMTION CD4352 Evaluation oa Hawae Switches Clocks/Data Heae S/PDIF Input (CS8416) Mux CS4352 nalog Output (Line Level) Muting Reset Reset Copyight Cius Logic, Inc (ll Rights Reseve) SEPTEMER '06 DS684D1

2 TLE OF CONTENTS CD CD4352 SYSTEM OVERVIEW CS4352 DIGITL-TO-NLOG CONVERTER CS8416 DIGITL UDIO RECEIVER INPUT FOR CLOCKS ND DT POWER SUPPLY CIRCUITRY GROUNDING ND POWER SUPPLY DECOUPLING HRDWRE CONTROL NLOG OUTPUT FILTERING PERFORMNCE PLOTS DESIGN NOTE SCHEMTICS REVISION HISTORY LIST OF FIGURES Figue 1. FFT (48 k, 0 )... 6 Figue 2. FFT (48 k, )... 6 Figue 3. FFT (48 k, No Input)... 6 Figue 4. FFT (48 k Out-of-an, No Input)... 6 Figue k, THD+N vs. Input Feq... 6 Figue k, THD+N vs. Level... 6 Figue k, Fae-to-Noise Lineaity... 7 Figue k, Fequency Response... 7 Figue k, Cosstalk... 7 Figue k, Impulse Response... 7 Figue 11. FFT (96 k, 0 )... 7 Figue 12. FFT (96 k, )... 7 Figue 13. FFT (96 k, No Input)... 8 Figue 14. FFT (96 k Out-of-an, No Input)... 8 Figue k, THD+N vs. Input Feq... 8 Figue k, THD+N vs. Level... 8 Figue k, Fae-to-Noise Lineaity... 8 Figue k, Fequency Response... 8 Figue k, Cosstalk... 9 Figue k, Impulse Response... 9 Figue 21. FFT (192 k, 0 )... 9 Figue 22. FFT (192 k, )... 9 Figue 23. FFT (192 k, No Input)... 9 Figue 24. FFT (192 k Out-of-an, No Input)... 9 Figue k, THD+N vs. Input Feq Figue k, THD+N vs. Level Figue k, Fae-to-Noise Lineaity Figue k, Fequency Response Figue k, Cosstalk Figue k, Impulse Response Figue 31. System lock Diagam an Signal Flow Figue 32. CS Figue 33. nalog Outputs Figue 34. PCM Input Heaes Figue 35. CS8416 S/PDIF Input Figue 36. Powe Figue 37. Silksceen Top DS684D1

3 CD4352 Figue 38. Top Sie Figue 39. ottom Sie LIST OF TLES Table 1. System Connections... 5 Table 2. CD4352 Jumpe Settings DS684D1 3

4 1. CD4352 SYSTEM OVERVIEW CD4352 The CD4352 evaluation boa is an excellent means of quickly evaluating the CS4352. The CS8416 igital auio inteface eceive povies an easy inteface to igital auio signal souces incluing the majoity of igital auio test equipment. The evaluation boa also allows the use to supply extenal PCM clocks an ata though a heae fo system evelopment. The CD4352 schematic has been patitione into five schematics, as shown in Figues 32 though 36. Each patitione schematic is epesente in the system iagam shown in Figue 31. Notice that the system iagam also inclues the inteconnections between the patitione schematics. 2. CS4352 DIGITL-to-NLOG CONVERTER esciption of the CS4352 is inclue in the CS4352 atasheet. 3. CS8416 DIGITL UDIO RECEIVER The system eceives an ecoes the stana S/PDIF ata fomat using a CS8416 Digital uio Receive, Figue 35. The outputs of the CS8416 inclue a seial bit clock, seial ata, left-ight clock, an a 128/256 Fs maste clock. The CS8416 ata fomat is fixe to I²S. The opeation of the CS8416 an a iscussion of the igital auio inteface is inclue in the CS8416 atasheet. The evaluation boa has been esigne such that the input can be eithe optical o coaxial, see Figue 35. Howeve, both inputs cannot be iven simultaneously. Position 2 of S1 sets the output MCLK to LRCK atio of the CS8416. This switch shoul be set to 256 (LO) fo input Fs<=48 k an can be eithe 256 (LO) o 128 (HI) fo Fs>48 k 4. INPUT FOR CLOCKS ND DT The evaluation boa has been esigne to allow intefacing to extenal systems via the heae J13. Heae J13 allows the evaluation boa to accept extenally geneate PCM clocks an ata. The schematic fo the clock/ata input is shown in Figue 34. Switch position 1 of S1 selects the souce as eithe CS8416 o heae J13. Please see the CS4352 atasheet fo moe infomation. 5. POWER SUPPLY CIRCUITRY Powe is supplie to the evaluation boa by thee bining posts (GND, VL, an V_H), see Figue 36. The VL supply can be jumpee to a +3.3 V egulato o povie extenally though the VL bining post. VD an V is nomally supplie by the 3.3 V egulato but can be isconnecte using J4 an J6 an then have extenal voltage applie to the VD an V test points. The +5 V supply (which powes the egulatos fo this boa) is nomally supplie by a 5 V egulato but can be supplie extenally by emoving J7 an applying 5 V to TP8. Powe consumption of the CS4352 can be measue though the voltage op at J8, J9, J10, an J11 when the shunts ae emove. WRNING: Refe to the CS4352 atasheet fo maximum allowable voltages levels. Opeation outsie of this ange can cause pemanent amage to the evice. 4 DS684D1

5 CD GROUNDING ND POWER SUPPLY DECOUPLING s with any high-pefomance convete, the CS4352 equies caeful attention to powe supply an gouning aangements to optimize pefomance. Figue 32 etails the connections to the CS4352 an Figues 37, 38, an 39 show the component placement an top an bottom layout. The ecoupling capacitos ae locate as close to the CS4352 as possible. Extensive use of goun plane fill in the evaluation boa yiels lage euctions in aiate noise. 7. HRDWRE CONTROL The CD4352 is contolle though settings on switch S1. This allows fo configuation of the boa without a PC. switch is povie fo CS8416 MCLK spee, clock an ata souce fo the boa, an the hawae moe configuation of the CS NLOG OUTPUT FILTERING The analog output on the CD4352 has been esigne accoing to the CS4352 atasheet. This output cicuit inclues an C coupling cap, the JT mute cicuit, an a single-pole R an C. CONNECTOR INPUT/OUTPUT SIGNL PRESENT VL Input V to +3.3 V powe fo the CS4352 seial inteface V_H Input +9 V to +12 V positive supply fo the CS4352 high-voltage analog an the CD4352 egulatos GND Input Goun connection fom powe supply SPDIF INPUT - J16 Input Digital auio inteface input via coaxial cable SPDIF INPUT - OPT1 Input Digital auio inteface input via optical cable PCM INPUT - J13 Input Input fo maste, seial, left/ight clocks an seial ata OUT an OUT Output RC line-level analog outputs Table 1. System Connections DS684D1 5

6 9. PERFORMNCE PLOTS CD Figue 1. FFT (48 k, 0 ) Figue 2. FFT (48 k, ) 0 0 Figue 3. FFT (48 k, No Input) 20k 40k 60k 80k 100k 120k Figue 4. FFT (48 k Out-of-an, No Input) 0 0 Figue k, THD+N vs. Input Feq 0 FS Figue k, THD+N vs. Level 6 DS684D1

7 CD FS -5 Figue k, Fae-to-Noise Lineaity Figue k, Fequency Response m V 0 0m u 1m 1.5m 2m 2.5m 3m sec Figue k, Cosstalk Figue k, Impulse Response 0 0 Figue 11. FFT (96 k, 0 ) Figue 12. FFT (96 k, ) DS684D1 7

8 CD k 40k 60k 80k 100k 120k Figue 13. FFT (96 k, No Input) Figue 14. FFT (96 k Out-of-an, No Input) FS Figue k, THD+N vs. Input Feq Figue k, THD+N vs. Level FS -5 Figue k, Fae-to-Noise Lineaity Figue k, Fequency Response 8 DS684D1

9 CD m V 0 0m u 500u 750u 1m 1.25m 1.5m sec Figue k, Cosstalk Figue k, Impulse Response 0 0 Figue 21. FFT (192 k, 0 ) Figue 22. FFT (192 k, ) k 40k 60k 80k 100k 120k Figue 23. FFT (192 k, No Input) Figue 24. FFT (192 k Out-of-an, No Input) DS684D1 9

10 CD FS Figue k, THD+N vs. Input Feq Figue k, THD+N vs. Level FS -5 Figue k, Fae-to-Noise Lineaity Figue k, Fequency Response m V 0 0m u 400u 600u sec Figue k, Cosstalk Figue k, Impulse Response 10 DS684D1

11 CD4352 JUMPER / SWITCH PURPOSE POSITION FUNCTION SELECTED J7 J4 J5 J6 Selects souce of voltage fo the +5V supplies Selects souce of voltage fo the VD supplies Selects souce of voltage fo the VL supply Selects souce of voltage fo the V supply +5 V *+5V_REG VD *+3.3V REG VL *+3.3V REG V *+3.3V REG J8 Cuent measue fo VD *shunte J9 Cuent measue fo VL *shunte J10 Cuent measue fo V *shunte J11 Cuent measue fo V_H *shunte S1 Sets clock souce, CS8416 clock spee, an CS4352 settings *1 = open *2, 3, 4, 5 = close Voltage souce is +5 V test point (TP8) Voltage souce is +5 V egulato Voltage souce is VD test point (TP2) Voltage souce is +3.3 V egulato Voltage souce is VL bining post Voltage souce is +3.3 V egulato Voltage souce is V test point (TP7) Voltage souce is +3.3 V egulato When shunt is emove, the voltage can be measue acoss a fixe esistance to etemine cuent. When shunt is emove, the voltage can be measue acoss a fixe esistance to etemine cuent. When shunt is emove, the voltage can be measue acoss a fixe esistance to etemine cuent. When shunt is emove, the voltage can be measue acoss a fixe esistance to etemine cuent. position 1: 0 = extenal clock souce, 1 = CS8416 position 2: 0 = 8416 MCLK is 256xFs, 1 = 128xFs Position 3,4,5: see CS4352 atasheet S2 Reset - Enables eset fo CS4352 an CS8416 when pesse J12 J17 Mute Disable *LED MUTE ypasses muting to tun on LED Nomal muting cicuit *Default Factoy Settings. Table 2. CD4352 Jumpe Settings 10.DESIGN NOTE 10.1 CD4352 Revision.0 D2 has been emove an shote an R2 has been emove. The seial auio ecoe table fo S1 is incoect. 01 shoul be RJ-24 an 10 shoul be LJ The polaity of the silksceen fo Z1, Z2, Z3, Z4, an Z5 is incoect The CS4352 evision is CD4352 Revision.0 No eos at this time DS684D1 11

12 12 DS684D1 11.SCHEMTICS 8416 Digital uio Receive Figue 35 PCM Inputs Figue 34 MCLK SCLK LRCK SDIN Reset Cicuit Hawae Switch Figue 34 CS4352 Figue 32 Powe Figue 36 Figue 31. System lock Diagam an Signal Flow Channel Outputs an Mute Figue 33 Channel Outputs an Mute Figue 33 CD4352

13 CD4352 Figue 32. CS4352 DS684D1 13

14 CD4352 Figue 33. nalog Outputs 14 DS684D1

15 CD4352 Figue 34. PCM Input Heaes DS684D1 15

16 CD4352 Figue 35. CS8416 S/PDIF Input 16 DS684D1

17 CD4352 Figue 36. Powe DS684D1 17

18 CD4352 Figue 37. Silksceen Top DS684D1 18

19 CD4352 Figue 38. Top Sie 19 DS684D1

20 CD4352 Figue 39. ottom Sie 20 DS684D1

21 12.REVISION HISTORY Release D1 Initial Release D2 e Pefomance Plots Changes CD4352 Contacting Cius Logic Suppot Fo all pouct questions an inquiies, contact a Cius Logic Sales Repesentative. To fin the one neaest you, go to IMPORTNT NOTICE Cius Logic, Inc. an its subsiiaies ("Cius") believe that the infomation containe in this ocument is accuate an eliable. Howeve, the infomation is subject to change without notice an is povie "S IS" without waanty of any kin (expess o implie). Customes ae avise to obtain the latest vesion of elevant infomation to veify, befoe placing oes, that infomation being elie on is cuent an complete. ll poucts ae sol subject to the tems an conitions of sale supplie at the time of oe acknowlegment, incluing those petaining to waanty, inemnification, an limitation of liability. No esponsibility is assume by Cius fo the use of this infomation, incluing use of this infomation as the basis fo manufactue o sale of any items, o fo infingement of patents o othe ights of thi paties. This ocument is the popety of Cius an by funishing this infomation, Cius gants no license, expess o implie une any patents, mask wok ights, copyights, taemaks, tae secets o othe intellectual popety ights. Cius owns the copyights associate with the infomation containe heein an gives consent fo copies to be mae of the infomation only fo use within you oganization with espect to Cius integate cicuits o othe poucts of Cius. This consent oes not exten to othe copying such as copying fo geneal istibution, avetising o pomotional puposes, o fo ceating any wok fo esale. CERTIN PPLICTIONS USING SEMICONDUCTOR PRODUCTS MY INVOLVE POTENTIL RISKS OF DETH, PERSONL INJURY, OR SEVERE PROP- ERTY OR ENVIRONMENTL DMGE ( CRITICL PPLICTIONS ). CIRRUS PRODUCTS RE NOT DESIGNED, UTHORIZED OR WRRNTED FOR USE IN IRCRFT SYSTEMS, MILITRY PPLICTIONS, PRODUCTS SURGICLLY IMPLNTED INTO THE ODY, UTOMOTIVE SFETY OR SECURITY DE- VICES, LIFE SUPPORT PRODUCTS OR OTHER CRITICL PPLICTIONS. INCLUSION OF CIRRUS PRODUCTS IN SUCH PPLICTIONS IS UNDER- STOOD TO E FULLY T THE CUSTOMER S RISK ND CIRRUS DISCLIMS ND MKES NO WRRNTY, EXPRESS, STTUTORY OR IMPLIED, INCLUDING THE IMPLIED WRRNTIES OF MERCHNTILITY ND FITNESS FOR PRTICULR PURPOSE, WITH REGRD TO NY CIRRUS PRODUCT THT IS USED IN SUCH MNNER. IF THE CUSTOMER OR CUSTOMER S CUSTOMER USES OR PERMITS THE USE OF CIRRUS PRODUCTS IN CRITICL PPLICTIONS, CUSTOMER GREES, Y SUCH USE, TO FULLY INDEMNIFY CIRRUS, ITS OFFICERS, DIRECTORS, EMPLOYEES, DISTRIUTORS ND OTHER GENTS FROM NY ND LL LIILITY, INCLUDING TTORNEYS FEES ND COSTS, THT MY RESULT FROM OR RISE IN CONNECTION WITH THESE USES. Cius Logic, Cius, an the Cius Logic logo esigns ae taemaks of Cius Logic, Inc. ll othe ban an pouct names in this ocument may be taemaks o sevice maks of thei espective ownes. DS684D1 21