AKD4341-SB AK4341 Evaluation Board Rev.0

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1 SHI KSEI [KD4341-S] KD4341-S K4341 Evaluation oa Rev.0 Geneal Desciption KD4341-S is an evaluation boa fo K4341 (192k sampling 24it ΔΣ DC). KD4341-S has a igital auio inteface (K4113) of Optical o COX input an can easily achieve the inteface with igital auio system. Theefoe, it is easy to evaluate the soun quality of K4341. Oeing Guie KD4341-S ---- K4341 Evaluation oa On-boa igital auio inteface. (K4113) Function NC Connecto NC Connecto COX In Opt In DIR K4113 K4341 Lch NC Connecto TORX193 Rch Figue 1. KD4341-S lock iagam (* Cicuit iagam ae attache at the en of this manual.) COX is ecommene fo an evaluation of the Soun quality. <KM087300> /03

2 SHI KSEI [KD4341-S] Opeation sequence 1) Set up the powe supply lines. (See Othe jumpes set-up.) Name of jack +9V (J4) +5V (J5) +3.3V (J6) GND (J7) GND (J8) Colo of jack Voltage Use fo Comments an attention Default setting Re V HVDD of K4341, This jack shoul be always connecte to powe supply. +9V Regulato T1 Re V TVDD of K4113, This jack shoul be always connecte to powe supply. +5V Logic cicuit VDD an DVDD This jack shoul be always connecte to powe supply. +3.3V Re V of K4341, Logic cicuit lack 0V GND This jack shoul be always connecte to powe supply. 0V This jack is use when the goun is sepaate. lack 0V GND Please set 0Ω jumpe of R28 fom R31 popely. Table 1. Set up of powe supply lines open Each supply line shoul be istibute fom the powe supply unit. 2) Set-up the jumpe pins 3) Set-up the DIP switches. (See the followings.) 4) Powe on The K4341 shoul be eset once by binging SW3 (PDN) L upon powe-up. <KM087300> /03

3 SHI KSEI [KD4341-S] Evaluation moe 1. Using DIR (COX) (efault) It is possible to evaluate the K4341 by using CD isk. The DIR geneates MCLK, ICK, LRCK an SDT fom the eceive ata though NC connecto (J3). Setting of jumpe is shown below. COX is ecommene fo an evaluation of the Soun quality. OPT JP3 COX (COX) (Default) Figue 2. Jumpe setting, when using DIR (COX) (efault) 2. Using DIR (Optical Link) It is possible to evaluate the K4341 by using CD isk. The DIR geneates MCLK, ICK, LRCK an SDT fom the eceive ata though optical connecto (PORT3: TORX193). Setting of jumpe is shown below. JP3 OPT COX (OPT) 3. ll clocks ae fe though the PORT1. Change the esistance as below. R5: 5.1Ω open R6, R7, R8: 100Ω open R1, R2, R3, R4: open 100Ω o shot (0Ω) Setting of DIP switch Figue 3. Jumpe setting, when using DIR (Optical Link) [SW1]: K4113 setting No. Pin OFF ON Default 1 OCKS1 K4113 Maste Clock setting ON 2 OCKS0 Refe to Table4 OFF Table 2. SW1 setting [SW2]: K4341 setting No. Pin OFF ON Default 1 CKS Manual Setting Moe uto Setting Moe ON 2 DIF uio ata fomat : MS justifie uio ata fomat : I 2 S Compatible OFF 3 DEM De-emphasis filte : Disable De-emphasis filte : Enable OFF Table 3. SW2 setting <KM087300> /03

4 SHI KSEI [KD4341-S] The fequency of the maste clock output is set by OCKS0 an OCKS1 as shown in Table 4. OCKS1 OCKS0 MCLK Fequency fs=32/44.1/48k 1 1 fs=176.4/192k Table 4. MCLK Clock Default Setting of SW3 (Setting of PDN of K4341) [SW3](PDN): Reset of K4341. Select H uing opeation. Setting of SW4 (Setting of SMUTE of K4341) [SW4](SMUTE): Soft-mute of K4341. Soft-mute is execute uing pushe. Setting of jumpe pin JP1 (Setting of GIN of K4341) [JP1](GIN): Output level of OUTL/OUTR pin of K4341 can be selecte by jumpe pin JP1 (GIN). (Fo futhe etails, please efe to atasheet of K4341.) GIN GIN (JP1) L 0 (Default) H +6 Open +12 Table 5. Setting of output level of OUTL/OUTR pin of K4341 <KM087300> /03

5 SHI KSEI [KD4341-S] Measuement Result [Measuement conition] Measuement unit MCLK ICK fs W Resolution Powe Supply Inteface Tempeatue GIN : uio Pecision SYS-2722 (192K) : 512fs (fs=44.1k), 256fs (fs=96k), 128fs (fs=192k) : 64fs : 44.1k, 96K, 192K : 20 20k (fs=44.1k), 20 40k (fs=96k, 192K) : 24bit : VDD=+5V, HVEE=-5V : K4113 (fs=44.1k, 96K, 192K) : Room Temp : L fs=44.1k Paamete Input signal Measuement filte Lch Results Rch Results S/(N+D) 1k, 0 20kLPF S/(N+D) 1k, 20kLPF DR 1k, 20kLPF, -weighte S/N 0 ata 20kLPF, -weighte fs=96k Paamete Input signal Measuement filte Lch Results Rch Results S/(N+D) 1k, 0 40kLPF S/(N+D) 1k, 40kLPF DR 1k, 40kLPF, -weighte S/N 0 ata 40kLPF, -weighte fs=192k Paamete Input signal Measuement filte Lch Results Rch Results S/(N+D) 1k, 0 40kLPF S/(N+D) 1k, 40kLPF DR 1k, 40kLPF, -weighte S/N 0 ata 40kLPF, -weighte <KM087300> /03

6 SHI KSEI [KD4341-S] Plots [Measuement Conition] Measuement Unit MCLK ICK fs W Resolution Powe Supply Inteface Tempeatue GIN : uio Pecision SYS-2722 (192K) : 512fs (fs=44.1k), 256fs (fs=96k), 128fs (fs=192k) : 64fs : 44.1k, 96k, 192k : 20 20k (fs=44.1k), 40 40k (fs=96k), 80 80k (fs=192k) : 24bit : VDD=+5V, HVEE=-5V : K4113 (44.1k, 96k, 192k) : Room Temp : L fs=48k Figue 8. FFT (Input Fequency =1k, Input Level =0FS) Figue 9. FFT (Input Fequency =1k, Input Level =FS) Figue 10. FFT (noise floo) Figue 11. FFT (out-of-ban noise) Figue 12. THD+N vs Input Level (Input Fequency =1k) Figue 13. THD+N vs Input Fequency (Input Level=0FS) Figue 14. Lineaity (Input Fequency =1k) Figue 15. Fequency Response (Input Level=0FS) Figue 16. Coss-talk (Input Level=0FS) fs=96k Figue 17. FFT (Input Fequency =1k, Input Level =0FS) Figue 18. FFT (Input Fequency =1k, Input Level =0FS,Notch-on) Figue 19. FFT (Input Fequency =1k, Input Level =FS) Figue 20. FFT (noise floo) Figue 21. FFT (out-of-ban noise) Figue 22. THD+N vs Input Level (Input Fequency =1k) Figue 23. THD+N vs fin (Input Level=0FS) Figue 24. Lineaity (Input Fequency =1k) Figue 25. Fequency Response (Input Level=0FS) Figue 26. Coss-talk (Input Level=0FS) fs=192k Figue 27. FFT (Input Fequency =1k, Input Level =0FS) Figue 28. FFT (Input Fequency =1k, Input Level =0FS,Notch-on) Figue 29. FFT (Input Fequency =1k, Input Level =FS) Figue 30. FFT (noise floo) Figue 31. FFT (out-of-ban noise) Figue 32. THD+N vs Input Level (Input Fequency =1k) Figue 33. THD+N vs fin (Input Level=0FS) Figue 34. Lineaity (Input Fequency =1k) Figue 35. Fequency Response (Input Level=0FS) Figue 36. Coss-talk (Input Level=0FS) FFT point=16384, vg=8, Winow=Equiiple <KM087300> /03

7 SHI KSEI [KD4341-S] (DC fs=44.1k) K4341 FFT HVDD=9V, VDD=3.3V, fs=44.1k, 0FS input k 2k 5k 10k 20k Figue 8. FFT(Input Fequency=1k, Input Level=0FS) K4341 FFT HVDD=9V, VDD=3.3V, fs=44.1k, FS input k 2k 5k 10k 20k Figue 9. FFT(Input Fequency=1k, Input Level=FS) <KM087300> /03

8 SHI KSEI [KD4341-S] (DC fs=44.1k) K4341 FFT HVDD=9V, VDD=3.3V, fs=44.1k, No signal input k 2k 5k 10k 20k Figue 10. FFT(noise floo) K4341 FFT Out of ban noise HVDD=9V, VDD=3.3V, fs=44.1k, No signal input k 2k 5k 10k 20k 50k 100k Figue 11. FFT(out-of-ban noise) <KM087300> /03

9 SHI KSEI [KD4341-S] (DC fs=44.1k) K4341 THD+N vs. Input Level HVDD=9V, VDD=3.3V, fs=44.1k, fin=1k FS Figue 12. THD+N vs Input Level (Input Fequency=1k) K4341 THD+N vs. Input Fequency HVDD=9V, VDD=3.3V, fs=44.1k, 0FS input k 2k 5k 10k 20k Figue 13. THD+N vs Input Fequency (Input Level=0FS) <KM087300> /03

10 SHI KSEI [KD4341-S] (DC fs=44.1k) K4341 Lineaity HVDD=9V, VDD=3.3V, fs=44.1k, fin=1k FS Figue 14. Lineaity (Input Fequency=1k).1 K4341 Fequency Response HVDD=9V, VDD=3.3V, fs=44.1k, 0FS input k 4k 6k 8k 10k 12k 14k 16k 18k 20k Figue 15. Fequency Response (Input Level=0FS) <KM087300> /03

11 SHI KSEI [KD4341-S] T -75 (DC fs=44.1k) K4341 Cosstalk (Re=Lch, lue=rch) HVDD=9V, VDD=3.3V, fs=44.1k, 0FS input k 2k 5k 10k 20k Figue 16. Coss-talk (Input Level=0FS) <KM087300> /03

12 SHI KSEI [KD4341-S] (DC fs=96k) K4341 FFT HVDD=9V, VDD=3.3V, fs=96k, 0FS input k 2k 5k 10k 20k 40k Figue 17. FFT(Input Fequency=1k, Input Level=0FS) K4341 FFT HVDD=9V, VDD=3.3V, fs=96k, 0FS input, Notch k 2k 5k 10k 20k 40k Figue 18. FFT(Input Fequency=1k, Input Level=0FS,Notch-on) <KM087300> /03

13 SHI KSEI [KD4341-S] (DC fs=96k) K4341 FFT HVDD=9V, VDD=3.3V, fs=96k, FS input k 2k 5k 10k 20k 40k Figue 19. FFT(Input Fequency=1k, Input Level=FS) K4341 FFT HVDD=9V, VDD=3.3V, fs=96k, No signal input k 2k 5k 10k 20k 40k Figue 20. FFT(noise floo) <KM087300> /03

14 SHI KSEI [KD4341-S] (DC fs=96k) K4341 FFT Out of ban noise HVDD=9V, VDD=3.3V, fs=96k, No signal input k 2k 5k 10k 20k 50k 100k Figue 21. FFT (out-of-ban noise) K4341 THD+N vs. Input Level HVDD=9V, VDD=3.3V, fs=96k, fin=1k FS Figue 22. THD+N vs Input Level (Input Fequency=1k) <KM087300> /03

15 SHI KSEI [KD4341-S] (DC fs=96k) K4341 THD+N vs. Input Fequency HVDD=9V, VDD=3.3V, fs=96k, 0FS input k 2k 5k 10k 20k 40k Figue 23. THD+N vs Input Fequency (Input Level=0FS) K4341 Lineaity HVDD=9V, VDD=3.3V, fs=96k, fin=1k FS Figue 24. Lineaity (Input Fequency=1k) <KM087300> /03

16 SHI KSEI [KD4341-S] (DC fs=96k).1 K4341 Fequency Response HVDD=9V, VDD=3.3V, fs=96k, 0FS input k 5k 7.5k 10k 12.5k 15k 17.5k 20k 22.5k 25k 27.5k 30k 32.5k 35k 37.5k 40k Figue 25. Fequency Response (Input Level=0FS) -75 K4341 Cosstalk (Re=Lch, lue=rch) HVDD=9V, VDD=3.3V, fs=96k, 0FS input k 2k 5k 10k 20k 40k Figue 26. Coss-talk (Input Level=0FS) <KM087300> /03

17 SHI KSEI [KD4341-S] (DC fs=192k) K4341 FFT HVDD=9V, VDD=3.3V, fs=192k, 0FS input k 2k 5k 10k 20k 50k 80k Figue 27. FFT(Input Fequency=1k, Input Level=0FS) K4341 FFT HVDD=9V, VDD=3.3V, fs=192k, 0FS input, Notch k 2k 5k 10k 20k 50k 80k Figue 28. FFT(Input Fequency=1k, Input Level=0FS,Notch-on) <KM087300> /03

18 SHI KSEI [KD4341-S] (DC fs=192k) K4341 FFT HVDD=9V, VDD=3.3V, fs=192k, FS input k 2k 5k 10k 20k 50k 80k Figue 29. FFT(Input Fequency=1k, Input Level=FS) K4341 FFT HVDD=9V, VDD=3.3V, fs=192k, No signal input k 2k 5k 10k 20k 50k 80k Figue 30. FFT(noise floo) <KM087300> /03

19 SHI KSEI [KD4341-S] (DC fs=192k) K4341 FFT Out of ban noise HVDD=9V, VDD=3.3V, fs=192k, No signal input k 2k 5k 10k 20k 50k 100k Figue 31. FFT(out-of-ban noise) K4341 THD+N vs. Input Level HVDD=9V, VDD=3.3V, fs=192k, fin=1k FS Figue 32. THD+N vs Input Level (Input Fequency=1k) <KM087300> /03

20 SHI KSEI [KD4341-S] (DC fs=192k) K4341 THD+N vs. Input Fequency HVDD=9V, VDD=3.3V, fs=192k, 0FS input k 2k 5k 10k 20k 50k 80k Figue 33. THD+N vs Input Fequency (Input Level=0FS) K4341 Lineaity HVDD=9V, VDD=3.3V, fs=192k, fin=1k FS Figue 34. Lineaity (Input Fequency=1k) <KM087300> /03

21 SHI KSEI [KD4341-S] (DC fs=192k).1 K4341 Fequency Response HVDD=9V, VDD=3.3V, fs=192k, 0FS input k 10k 15k 20k 25k 30k 35k 40k 45k 50k 55k 60k 65k 70k 75k 80k Figue 35. Fequency Response (Input Level=0FS) -75 K4341 Cosstalk (Re=Lch, lue=rch) HVDD=9V, VDD=3.3V, fs=192k, 0FS input k 2k 5k 10k 20k 50k 80k Figue 36. Coss-talk (Input Level=0FS) <KM087300> /03

22 SHI KSEI [KD4341-S] Revision Histoy Date (YY/MM/DD) Manual Revision oa Revision Reason 07/03/08 KM Fist Eition Contents IMPORTNT NOTICE These poucts an thei specifications ae subject to change without notice. efoe consieing any use o application, consult the sahi Kasei Micosystems Co., Lt. () sales office o authoize istibuto concening thei cuent status. assumes no liability fo infingement of any patent, intellectual popety, o othe ight in the application o use of any infomation containe heein. ny expot of these poucts, o evices o systems containing them, may equie an expot license o othe official appoval une the law an egulations of the county of expot petaining to customs an taiffs, cuency exchange, o stategic mateials. poucts ae neithe intene no authoize fo use as citical components in any safety, life suppot, o othe haza elate evice o system, an assumes no esponsibility elating to any such use, except with the expess witten consent of the Repesentative Diecto of. s use hee: (a) haza elate evice o system is one esigne o intene fo life suppot o maintenance of safety o fo applications in meicine, aeospace, nuclea enegy, o othe fiels, in which its failue to function o pefom may easonably be expecte to esult in loss of life o in significant injuy o amage to peson o popety. (b) citical component is one whose failue to function o pefom may easonably be expecte to esult, whethe iectly o iniectly, in the loss of the safety o effectiveness of the evice o system containing it, an which must theefoe meet vey high stanas of pefomance an eliability. It is the esponsibility of the buye o istibuto of an pouct who istibutes, isposes of, o othewise places the pouct with a thi paty to notify that paty in avance of the above content an conitions, an the buye o istibuto agees to assume any an all esponsibility an liability fo an hol hamless fom any an all claims aising fom the use of sai pouct in the absence of such notification. <KM087300> /03

23 J4 J5 J6 J7 J8 +9V +5V +3.3V GND GND SW1 OCKS VCC T (Re) T (Re) T (Re) T (lack) T (lack) VCC +3.3V OCKS1 OCKS HVDD VCC +3.3V D C19 10u R C6 0.1u C7 0.1u U2 DVDD DVSS TVDD V/TX XTI XTO CM0/CDTO/CD1 30 CM1/CDTI/SD 29 OCKS1/CCLK/SCL 28 OCKS0/CSN/CD0 27 MCKO1 26 MCKO2 25 R21 R22 47k 47k R5 51 R6 100 DSS102 R1 R2 (open) (open) MCLK ICK LRCK SDT PORT1 DSP C25 470u R18 (shot) R19 (shot) C22 47u C24 47u GND1 + C10 0.1u + 1 T1 upc3533hf IN GND 2 OUT C21 47u 3 + C11 0.1u C23 47u + R16 R28 0 R29 0 (shot) GND2 VDD R30 0 GND1 R31 (open) D C COX GND2 J3 NC-R-PC GND2 PORT2 DIR GND2 6 6 OUT 1 GND 2 VCC GND 4 TORX193 PDN_ V C18 10u C9 0.1u R27 75 COX OPT + R26 0 GND2 + C8 0.1u R23 15k JP3 RX 0.1u C5 VCC VCC L1 47u C20 10u PDN R VDD VSS RX1 RX2/DIF0 RX3/DIF1 RX4/DIF2 RX5 K4113 R11 10k VCC D1 HSU119 DUX 24 ICK 23 SDTO 22 LRCK 21 INT0 20 FS96/I2C 19 P/SN 18 INT1 17 RX6/IPS 16 VCC R7 100 R8 100 TEST1 INT0 TEST2 INT1 +3.3V R14 R15 10k 10k R25 15k R3 R4 R24 15k (open) (open) C1 10p C2 (open) 1P-2.54DS MCLK ICK SDTI LRCK PDN SMUTE CKS DIF U1 K4341 GIN 16 VCOM 15 VDD 14 JP1 GIN C28 C4 0.1u H L + C15 10u R13 10k VDD HVDD +3.3V C16 R C26 2.2n C27 2.2n OUTL OUTR C LOW HI VSS 13 HVDD 12 OUTL DEM 9 11 OUTR 10 C3 0.1u + 10u + C14 10u u C17 10u R9 470 J1 J2 NC-R-PC NC-R-PC C13 0.1u SW3 PDN RP CKS 1 DIF 2 DEM V SW2 MODE SW1 OCKS1 OCKS0 Maste Clock VCC R12 10k SW4 SMUTE VCC C12 0.1u U3 1 1Y 2 2 2Y 4 3 3Y 6 4 4Y 8 5 5Y Y 12 VCC GND 74HC14 M5-13J PDN_4113 DSS104 L L L H 256fs@fs=88.2k/96k Don't use H L 512fs@fs=32k/44.1k/48k H H 128fs@fs=176.4k/192k Title KD4341-S Size Document Numbe Rev 3 KD4341-S Date: Tuesay, Febuay 06, 2007 Sheet 1 of 2 1

CDB4352. Evaluation Board for CS4352 CS4352. Description. Features. Demonstrates Recommended Layout And Grounding Arrangements

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