Summary of SNAP thermal tests

Transcription

1 Summary of SNAP thermal tests Rich Lacasse Aug. 4, 2016 Introduction In late July and early August of 2016 a series of tests were run to measure the thermal properties of the SNAP board in the RFI case designed by NRAO. This report summarizes these tests. It is organized into three sections. First, a summary of the equipment used is presented. Second, a table summarizing the results is presented. Third, a running log of the tests is presented; this includes a number of screen shots of power system and FPGA temperatures, photos of the configuration and IR photos. It is interesting to note that the first six tests were done without a clock connected to the SNAP. This gives a measure of the heating that occurs due, I assume, to leakage current in the FPGA. It is not insignificant! Equipment: Infrared camera: FLIR E30 IM2300-C-00009, s/n Air velocity meter Airdata ADM-880C with airfoil probe Signal generator: HP 8654A Bench supply: Tenma Fan: muffin fan, no part number; air velocity ~ 2.5 meters/s = ~200 feet/min FPGa Personality: HERA:snap_fengine, available at Room temperature ~ 22 o C Test Summary Number Configuration Current FPGA Temp. Regulator Temp. 1 1 Board on Bench; no clock; fan on; 0.9A heat sink on but its fan is removed. 2 Board on Bench; no clock; fan off 0.9A Mounted in box with top cover off 0.9A and bottom heat block installed; no clock; heat sink totally removed; 4 Mounted in enclosure; cover off, external fan on. Board mounting screws installed. DB-15 installed. SMA ports covered with copper tape. 0.9A

2 5 As with Test 4 except top cover is installed without the metal block mounted to the cover; fan on. 6 As with Test 5 but with metal block installed inside the top cover. Fans is off SNAP mounted in RFI case, cover 1.6A off, fan on, clock input powered. Case raised 0.5 above table to allow airflow underneath 8 SNAP mounted in RFI case, cover off, fan on, clock input powered. Case raised 0.5 above table to allow airflow underneath 9 Test in vertical orientation with the power regulators higher than the FPGA. Fan on, clock on 10 As in test 8, but with fan off / / 76 1 The temperature of UCD9248@52d which is the, in most cases, the warmest-running monitored component in the power regulator system. 2 Temperature slowly climbs, about a degree every five minutes. The 66.1 o was after 30 minutes. It was 68.9 after one hour. The entire case feels warm to the touch; this is the only test in which this occurred. The max operating junction temperature specification of the UCD9248 and the Kintex chip is 125 o C. Test Log Test 1 Configuration: SNAP on anti-static mat. Fan removed from FPGA heat sink. Muffin fan blowing across board. System draws 0.9A at 12.0 volts. Air velocity over the FPGA is about 2.5 m/s.

3 SNAP draws about 0.9A. Power summary: Fusion dashboard FPGA temperature:

4 IR camera: ] Test 2 Just like Test 1 except power off the fan and let the temperatures stabilize Power summary: Fusion dashboard

5 FPGA Temperature: IR Camera:

6 Test 3 In enclosure with heatsink removed; bottom heat block installed; external fan on. Figure 1. View of box with bottom heat sink and thermal pad installed.

7 Figure 2. View of board after heat sink removal. Note that the lid came off the chip and that decoupling capacitors are visible.

8 Figure 3. View of the board with FPGA lid replaced. There are notches at the corners of the lid that register the lid with the die carrier. Quick functional test since the heat-spreader lid came off the FPGA. Assure that the temperatures stay reasonable. Keep the large fan on.

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10 The IR image above does not show the expected heat pattern on the FPGA. It should be warmer in the center, where directly over the die. Instead it appears warmer on the leeward side of the fan. This is due to some residual adhesive from the heat-sink; the adhesive must have a different emissivity from the rest of the lid. Above screenshots were taken about 5 minutes after the SNAP was powered up. Let it run another 10 minutes or so while monitoring the temperature. After 15 additional minutes the temperature reads C. Test 4 SNAP mounted in enclosure; cover off, external fan on. Board mounting screws installed. DB-15 installed. SMA ports covered with copper tape. Now screw the board into the case and install the DB-15 in the case. Now it has better thermal contact with the case.

11 Monitor the temperature with the cover off and the external fan on. After about 20 minutes we see:

12 So it is doing slightly better than before. It turns out that the hot spots on the edge of the FPGA s top correspond to the adhesive that remained on the cover from the thermal pad for the heat sink. Test 5 As with Test 4 except top cover is installed without the metal block mounted to the cover Since it is operating at a very reasonable temperature so far, put the cover on without the metal block that contacts the FPGA Leave the external fan on

13 Note the empty screw holes for the metal block in the lid. The temperature stayed at around 38 degrees C for about 10 minutes and then vivado lost contact with the target. Restart vivado. Still no contact. Power down. Remove the lid. Disconnect the JTAG. Power up while observing the LEDs. They do their normal thing Try to connect and it does. T = 34.2 o C. Put the cover back on, all 22 screws! After about 5 minute, take an IR picture of the case:

14 The holes for the metal block in the lid are clearly seen. After about 10 minutes capture the FPGA and power system monitor screens:

15 Turn off the fan After about 5 minutes, the FPGA temp climbs to The power supply temperatures also go up by one or two degrees. Capture screens and images after 15 minutes:

16 To the touch, everything feels about the same temperature, almost room temperature. Some of the differences we see may be due to the emissivity of the various materials. The slightly warmer spots in the lid, near the mounting holes for the heat-sink block are pencil markings showing the directions that the holes need to be moved to get perfect alignment between the heat sink and the FPGA. There is clearly a thermal gradient on the ribbon cables. Peak to peak variation in the photo is only 12 degrees Fahrenheit. Shut down for the weekend! Glue the lid back onto kintex using Loctite 426 adhesive. Test the system. It operates as it did last week. Test 6 Install the aluminum block on the lid. Install the lid on the case. At this point, both thermal shorts to the lid are installed. Monitor the temperatures for 15 minutes with the external fan OFF.

17 After 20 minutes:

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19 Test 7 SNAP mounted in RFI case, cover off, fan on, clock input powered. This is the first test where the clock input was powered. Measure clock power and frequency with oscilloscope (TEK ) Per the schematic, desired input power is +2 dbm which is equivalent to Vpp. Measure the power at the end of the cable used to connect the signal generator to the SNAP enclosure.

20 Above corresponds to 1.92 dbm, close enough to 2. The meter on the signal generator reads 0.32 volts. This is not too unreasonable since it has not been calibrated in decades and there is loss in the cable Power up with 250 MHz clock: The 12-volt current goes to 1.6 A as Jack Hickish had predicted. Initially test with cover off and external fan on. Although not obvious in the photo below, the case is raised about 0.5 above the table to allow airflow underneath it as well. FPGA temperature almost immediately goes to 53.6 and then slowly climbs.

21 Above image is about 6 minutes after power up. Note that ADCs are warm; they were not when no clock was provided in the previous tests. FPGA lid does not look warm. It may be reflective at IR or have a very different emissivity?? Fortunately, we can read the die temperature directly:

22 Above screen-shots are about 8 minutes after power up. After 17 minutes:

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24 Monitor for until 30 minutes have elapsed

25 Very little difference! Test 8 Now install the cover with the aluminum block in it:

26 Note that aluminum block is slightly offset from FPGA. Per Bob Treacy it needs to be moved 131 mils to the left and 116 mils forward. The offset should be inconsequential for this test. The external fan is on. After 5 minutes the FPGA temp is C. After 20 minutes:

27 Above: from a distance at an angle

28 Above: From the regulator and ZDOK connector side. 10 GbE transceiver

29 From the short side with the power regulators. Crinkly stuff on the left is copper tape. Test 9 Test in vertical orientation with the power regulators higher than the FPGA:

30 RFI case is propped up with a copper bar. Fan is raised to be on about the same level as the FPGA. After about 22 minutes:

31 Looking at the top of the RFI case Looking at the bottom of the RFI case,, partially obstructed by the copper bar used to prop up the case. Note that the copper bar used for support is reflective of the IR: we see a reflection of the fan in it.

32 One could try testing without the aluminum blocks, but I don t want to take the risk! 8/4/2016 Repeat the test where the SNAP is in the RFI case, the case is closed and the clock is powered up. We get about the same result as yesterday:

33 Above screenshots taken after 27 minutes of stabilization. Test 10 Now power down the fan and closely monitor the temperature. Clock is running. The temperature shoots up to about 60 degrees quickly and then slowly continues to rise. It rises almost 3 degrees between 30 and 60 minutes into the test. The test was stopped shortly after taking the following data. After one hour:

34 The max junction temperature of the power regulator chip, UCD9248, and of the Kintex, is 125 o C. We are still a long way from that. The case feels quite warm to the touch.

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