Research Article Reconfigurable and Reusable Mutual Module Based Parameterization Approach for DWT and FFT Algorithm

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1 Research Journal of Applied Sciences, Engineering and Technology 7(22): , 2014 DOI: /rjaset ISSN: ; e-issn: Maxwell Scientific Publication Corp. Subitted: Noveber 07, 2013 Accepted: Deceber 09, 2013 Published: June 10, 2014 Research Article Reconfigurable and Reusable Mutual Module Based Paraeterization Approach for DWT and FFT Algorith 1 J. Venkatesh and 2 R. Rani Heaalini 1 St. Peter`s University, 2 Departent of ECE, St. Peter`s College of Engineering and Technology, Avadi, Chennai , India Abstract: Goal of this research article is to study and the analysis of a paraeterization technique called Coon Operator for an ebedded digital signal processing syste and ipleentation of that ebedded syste using a special architecture to achieve better perforance. This can be realized by efficient hardware design with reduced area and low-power dissipation which is a significant challenge for ebedded systes, particularly in portable devices. The challenge is even ore pronounced when DWT and FFT with large transfor lengths need to be realized in ebedded hardware for several ebedded signal processing applications. When it coes to iniaturization or reuse or sharing of the hardware, two Paraeterization approaches, viz; the Coon Function approach and the Coon Operator approach are the effective ones. But in this study, it is proposed a reconfigurable FFT (Fast Fourier Transfor) operator using the coon operator approach. This operator can be reconfigured to switch fro an operator dedicated to copute the FFT to an operator which coputes the FFT in order to perfor DWT. Contribution of this study is to Miniize the waste of resources by odifying slightly the FFT butterfly to support the DWT coputation and to reduce the resources allocated to the reconfiguration, Siplify the reconfiguration between the two algoriths, by separating the calculation of the Real and Iaginary parts of FFT odules. Keywords: DWT-lifting, FFT-butterfly, utual odule, paraeterization INTRODUCTION Currently, ebedded systes have widely spread over consuer, coercial and ilitary applications. Ebedded systes have two fundaental characteristics viz; Reactive and Real-tie. Ebedded Digital Signal Processing (EDSP) systes is one of the iportant applications of real-tie ebedded syste, which uses a special architecture to achieve better perforance. Moreover, ebedded systes are widely used in standard applications such as wireless counication protocols deanding Orthogonal Frequency Division Multiplexing (OFDM) and radar iage processing or say iage processing. However, efficient hardware realization with reduced area and low-power dissipation is a significant challenge for ebedded systes, in particular portable devices. The challenge is even ore pronounced when DWT and FFT with large transfor lengths need to be realized in ebedded hardware for the application in wireless counication systes/counication systes such as in OFDM, odulation, channel coding, equalization, thresholding/denoising etc. The coon functions can be distinguished and then used to greatest advantage fro the Sharing of coon attributes aong the architectures in order to iprove power efficiency and area. Hence, the goal intended to be attained is a hardware efficient utual odule for DWT and FFT architectures, stressing on copact and low-power ebedded realizations. Recently, the paraeterization techniques have been introduced Naoues et al. (2010, 2011a), which identifies the coon prospects aidst the targeted standards with the objective of defining a capable operation to handle the required tasks. These operations when ade a slight change to their paraeters can switch fro a configuration to another. With the fast and growing interest in VLSI technology, various techniques have been presented on FPGA platfor to iprove the perforance of the ebedded hardware. In this study, a Paraeterization technique is used to greatest advantage, called the Mutual odule for Discrete Wavelet Transfor (DWT) and Fast Fourier Transfor (FFT) algoriths that can be considered to build a large range of counication standards. The fundaental concept behind the Mutual odule approach is to distinguish the coon eleents in couple of architectures that could be to a great extent reprocessed across two or ore distinct standards. Therefore, the Mutual odule approach stay standard independent such that, when required the utual odule for particular function is ipleented and Corresponding Author: J. Venkatesh, St. Peter`s University, Avadi, Chennai , India This work is licensed under a Creative Coons Attribution 4.0 International License (URL:

2 executed. And with iniization in area on chip, the signal processing function will characterize the Mutual odule. The work presented in this study will be to share two ost iportant and functionally different algoriths ipleented in wireless counication systes viz., FFT and DWT algoriths. Where, FFT algorith is usually utilized for decoding or ulticarrier odulation in OFDM along with DWT algorith preferred in thresholding (wavelet thresholding) or in Multicarrier Modulation in OFDM (MCM-OFDM). In this study, i have developed a Mutual Module based paraeterization approach for DWT and FFT algorith. The two distinct algoriths sharing the ipleentation odule under the paraeterization context are FFT and DWT algoriths. If the processed data and functions perfored by the DWT and FFT algoriths are copared, they see to be totally unlike. Therefore, a coon function can t be recognized and hence in the coon operator based paraeterization approach for DWT and FFT algorith is considered to enhance the design of the syste which can perfor both FFT and DWT operation by executing the one coon architecture for FFT and DWT algorith instead of executing both individually. The syste proposed in this study will be a reconfigurable cell that can be reused to perfor the operations of both DWT and FFT algorith. Contribution of this article is to iniize the waste of resources by odifying slightly the FFT butterfly architecture to support the DWT coputation architecture and to reduce the resources allocated to the reconfiguration cell. The reconfiguration between the two algoriths is siplified by separating the coplex valued FFT architecture into Real and Iaginary parts of the FFT odule. The Reconfigurable Mutual Module based paraeterization approach for DWT and FFT algorith design alike the existing coon operator techniques will provide effective results in ters of Area required and power consued by the traditional FFT and DWT architectures. LITERATURE REVIEW The study of Coon Operator approach is introduced in the literature. In this section a review on recent developent in Coon Operator approach is presented as, Naoues et al. (2011a) presented a coon butterfly for the FFT and Viterbi algoriths. They investigated where reuse and power consuption is traded against throughput. Perforance coparisons with siilar works are also discussed. Al-Ghouwayel et al. (2012) presented a reconfigurable Triple ode Multiplier that constitutes the core of the Butterflybased FFT. A scalable and flexible unit for the polynoial reduction needed in the Galois Fields-GF (2^) ultiplication is also proposed. An FPGA Res. J. App. Sci. Eng. Technol., 7(22): , ipleentation of the proposed ultiplier is given and the easures show a gain of 18% in ters of perforance-to-cost ratio copared to a Velcro approach where two self-contained operators are ipleented separately. Gul et al. (2007) presented a ethod for designing flexible ulti-standard radio systes. Their work consisted in exploring the design of ulti-standard systes at different levels of granularity and selected the convenient level depending on each designer's needs. It consisted first in aking a graph description of the ulti-standard syste to be designed. Then, an architectural exploration extracted the operators of a given ulti-standard device. These operators were requested to have enhanced reconfiguration capabilities so that a fast reconfiguration was ipleentable. Their study illustrated two scenarios of ulti-standard radio syste designs. Furtherore their approach presented the scheduling issues. Naoues et al. (2010) presented a coon structure for the FFT and Viterbi algoriths. A key benefit of exhibiting coon operators was the regular architecture it brings when ipleented in a Coon Operator Bank (COB). This regularity ade their architecture open to future function apping and adapted to accoodate silicon technology variability through dependable design. They also discussed the Global coplexity ipact. Naoues et al. (2011b) presented the Coon Operator technique to present new coon structures for the FFT and FEC decoding algoriths. A key benefit of exhibiting coon operators was the regular architecture it brings when ipleented in a Coon Operator Bank (COB). This regularity ade the architecture open to future function apping and adapted to accoodate silicon technology variability through dependable design. Alaus et al. (2010) elaborated the Coon Operator (CO) technique, which defined a ulti standard terinal, based on a liited set of Coon Operators. Their approach enhanced the reconfigurability and the scalability of the design but lead to a coplex anageent of data dependencies and scheduling of each operator for its correct execution in the terinal. They presented a Organization in Bank (COB) not only to itigate the scheduling issue but also to aintain the flexibility and the optiization in their technique. The COB benefits fro the property of the CO though liiting the ain part of the scheduling. The COB created a scalable design, liited the scheduling and reduced the nuber of operators. Applied in the case of LFSR targets to a tri-standard terinal, it lowers the hardware coplexity by up to 40%. Takala and Konsta (2006) presented partial-colun radix-2 FFT processors and realizations of butterfly operations. The area and power-efficiency of butterfly units to be used in their processor organization based on

3 bit-parallel ultipliers, distributed arithetic and CORDIC were analyzed and copared. Their processor organization perits the area of the FFT ipleentation to be traded against the coputation tie. The power consuption coparisons proved that butterflies based on bit-parallel ultipliers were powerefficient but have liitations on clock frequency. Butterflies based on distributed arithetic were used for higher clock frequencies. If extreely long FFTs are needed, then CORDIC based butterflies are applicable. Alaus et al. (2009) presented paraeterization as a digital radio design ethodology. Two different techniques, naely coon functions and coon operators were considered. The second view of their work was developed and illustrated with two exaples: the well-known Fast Fourier Transfor (FFT) and the Reconfigurable Linear Feedback Shift Register (R-LFSR), derived fro the classical Linear Feedback Shift Register (LFSR) structure. Motivation of research: Recently, the paraeterization techniques have been introduced (Naoues et al., 2010, 2011a), which identifies the coon prospects aidst the targeted standards with the objective of defining a capable operation to handle the required tasks. These operations when ade a slight change to their paraeters can switch fro a configuration to another. With the fast and growing interest in VLSI technology, various techniques have been presented on FPGA platfor to iprove the perforance of the ebedded hardware. In literature there have lot of works presenting Paraeterization approach, called the coon operator Technique for Viterbi and FFT algorith. This approach was to design the two distinct algoriths sharing the ipleentation odule under the paraeterization context are FFT and Viterbi algoriths. And ean while the work presented by Naoues et al. (2011a) otivated e to think further over ipleentation of coon operator and hence i have decided to enhance the design in coon operator based paraeterization approach for DWT and FFT algorith. The work in this study will be to design a reconfigurable cell that can be reused across these functions of DWT and FFT algorith. Contribution of this study is to Miniize the waste of resources by odifying slightly the FFT butterfly to support the DWT coputation and to reduce the resources allocated to the reconfiguration, Siplify the reconfiguration between the two algoriths, by separating the calculation of the Real and Iaginary parts of FFT odules. The Reconfigurable Mutual Module based paraeterization approach for DWT and FFT algorith design alike the existing coon operator techniques will provide effective results. The Reconfigurable Mutual Module based architecture proposed will be designed in Verilog and ipleented will be synthesized in Xilinx ISE tool. PROPOSED METHODOLOGY DWT and FFT algoriths appear to be entirely different in their approach, inters of processed data and functionality. Yet, if the syste paraeters are exained inutely, ipleentation/architectural reseblances could be identified in the Lifting and butterfly structures of DWT and FFT respectively. The DWT and FFT structures are researched in the following paragraphs for their architectural siilarity. Fig. 1: N-point radix-2 FFT architecture constituted by several butterfly eleents 4708

4 Fig. 2: A 2-point radix-2 FFT butterfly eleent FFT algorith, its review and proposed approach: DFT is one of the best transfor of its kind. DFT perfors Fourier Anlysis. DFT to a great deal is coputed using FFT. This is because the coputation tie consued by DFT to perfor the arithetic operations is ore while the sae arithetic operations perfored by FFT consues less coputational tie: N j. N Xl x. e, l 0,..., N 1, where x0,... xn 1 arecoplex nubers (1) Of any algoriths presented for FFT. Cooley and Tukey (1965) algorith is ost significantly utilized to decopose the transfor by size N/r at every phase for preferred radix-2. The decoposed transfor constitute as saller eleents called Butterfly structure/eleent. The cobination of all these sall eleents for FFT coputation is called as FFT butterfly of size r. The nae butterfly is derived fro the structure reseblance of the processing eleent of the Radix FFT architecture as in Fig. 1. In this study, radix-2 cooley-tukey FFT algorith is presented. The N-point FFT can be presented as 2^npoint FFT size and to do so a radix-2 cooley-tukey algorith is utilized. A Radix-r cooley-tukey algorith based N-FFT algorith is expressed in Eq. (1). Therefore the N-point FFT by adopting radix-2 cooleytukey algorith requires results of only two-n/2 Fourier transfors, thereby divide and conquer schee is applied to the input signal to obtain even and odd eleents. This is expressed in Eq. (2). The sketch below in Fig. 2 represents the butterfly eleent of the radix-2 cooley-tukey FFT algorith. The atheatical coputation of FFT butterfly structure resebles as in Fig. 2: X ( N /2) 1 p0 N1 q0 x x * e q 2 p * e 2. j. q. N 2. j.2 p. N ( N /2) 1 p0 x (2 p1) * e 2. j. 2. p. 1. N (2) 4709 Fig. 3: A 2-point FFT butterfly realization (Al Ghouwayel et al., 2012) The scheatic sybol presented for butterfly eleent anages to draw the perforance required for a Radix-2 FFT ipleentation. Fro the butterfly eleent presented in Fig. 2, it is observed that each of the processing eleents of Radix-2 FFT is constituted by an adder, a subtract and a ultiplier. This addsubtract and ultiply unit perfors atheatical coputation on the coplex values. The atheatical odel of coplex valued FFT operation can be expressed in general for as in Eq. (3). The general for of Eq. (3) Naoues et al. (2010) defines real and iaginary paraeters of the butterfly eleent. Input to the butterfly eleent is expressed as below: 1 x A jb 0 x E jf coplex FFT inputs w n C jd (3) Output of the butterfly eleent for the coplex input paraeters is expressed as: y y w n E CA DB j. F DA CB w n E CA DB j. F DA CB x x x x (4) To down play the coputational coplexity for designing the butterfly eleent Eq. (4) can be Rearranged (Naoues et al., 2010). In Eq. (4) the atheatical representation of bitterfly eleent is recorde, which when odeled will require 6 addsubtract units and 4-ultipliers. Thus by rearranging Eq. (4) as in Eq. (5), we reduce the odel coplexity and thus requires less ultipliers than the previous representation. The rearranged expression helps iniize architecture/ hardware coplexity by reducing ultipliers in the architecture. According to Eq. (5) it will require 9 add-subtract. This is sketched in Fig. 3: y y 0 1 E C. A B C D j. F C. A B D C E C. A B C D j. F C. A B D C (5)

5 Fig. 4: Lifting schee based DWT block scheatic Two perforance easures viz; Predict (Prial) and Update (Dual) lifting steps To execute DWT with lifting technique a couple of arithetic operations are required Noralization of the Dual and Prial lifting outcoes With lifting technique it is easier to supervise the boundary extension: Fig. 5: Conventional representation of coputational unit (processing eleent) for the lifting based DWT P z l1 1 h ( z i ( z ) 1 k 1 l 1 l ) k (6) Fig. 6: Proposed graphical representation of the MCU for the lifting based DWT DWT algorith, its review and proposed approach: Interpretation of a signal in tie-frequency doain is practiced by Discrete Wavelet Transfor (DWT). DWT is preferred because it is ipleented using a siple and effective approach of tree structured filter banks. In this study, since we are utilizing the lifting DWT, this part of the section reviews lifting DWT. To design the tree structured two channel filter banks, lifting schee is preferred because of its fast and efficient approach. Prial and Dual lifting are the two perforance easure of lifting schee along with splitting operation. The prial lifting step is also referred to as Update operation, while the Dual lifting step is referred to as Predict operation. The lifting based DWT scheatic presented in Fig. 4 defines the atheatical odel of the Eq. (6) and also describes the coputation techniques having three lifting steps respectively. The Lifting eleent/processing eleent presented in Fig. 4 is usually constitutes by Multiply Accuulate unit (MAC), but here we refer it as Main Coputation Unit (MCU) which is defined siilarly by Tseng et al. (2002). Matheatical expression for the sae is recorded in Eq. (7) to (10), while the odel design for the MCU is sketched in Fig. 5 and processing eleent based on MCU is sketched in Fig. 6. The coplete Data Flow Hardware design of the Lifting DWT for 9/7 filter is represented in Fig. 7: (7) (9) P U Y Y Y Y n H L n H L X 1 X 2 P U n n U X 0 X 2 predict P P update 0 U K * Y H 1 * Y K 1 n n Y Y lowpass H n 1 H n L highpass scaling (8) Characteristics of lifting DWT: X 0 X MCU R X1 co* 2 Factorizing a polyphase atrix into a sequence of The processing eleent initially, adds the sapled upper and lower triangular atrices and a constant even inputs, then ultiplies it with the polyphase filter diagonal atrix coefficient and at last the odd sapled input signal is 4710 (10)

6 added. This can be clearly understood fro the Eq. (10). Fig. 7: Data flow diagra for the (9/7) lifting based DWT Throughout this section we reviewed the FFT and DWT structure for its realization on FPGA platfor. Also, we outline a approach to realize FFT and DWT as a coon operator under paraeterization technique. Here, we have configured the processing eleents in such a way that, it eets the coon operator requireents. We call it as utual odule; this is because the processing eleent of the FFT (radix-2 cooley-tukey algorith) shares its processing eleents or configuration to perfor DWT operation (lifting DWT processing eleent). The utual odule is discussed in the next part of this section. Reconfigurable and reusable utual odule for DWT and FFT algoriths: Now in this part we discuss the ipleentation of the two algoriths DWT and FFT adopting paraeterization approach. Mutual Module for DWT and FFT is configured using paraeterization based coon operator technique. It is successfully executed by dividing the FFT outputs as real part of a pair of output and iaginary pair results. Now, the DWT processing eleent i.e., MCU output is either detail coefficient or coarse coefficient. Therefore, we have pinned down this as expression for better understanding: FFT _ butterfly_ eleent_ o/ p 1 E. j F. j F C. A B D C FFT _ butterfly _ eleent _ o / p 2 E C. A B D C C. A B C D C. A B C D Actually_ FFT _ butterfly_ o/ p [ real] j[ iaginary] real _ part E C. A B C D, and 4711 Fig. 8: Mutual odule for DWT and FFT algoriths A B A D C iaginary _ part F C.. The underlined paraeters are uncoon in real part and iaginary part, while C (A+B) is coon and this can be utilized as coon operator: where _ MCU _ o / p MCU X1 co * X 0 X 2 Therefore, MCU is realized by either Real apart or Iaginary part of butterfly eleent: = E C. A B C DorF C. A B D C [ D C C. A B] or C D C. A B ] [ X1 ( co*( X 0 X 2))] Coparing [ Now, the utual odule representation will be configured as in Fig. 8.

7 Fig. 9: Proposed reconfigurable and reusable utual odule for DWT and FFT algoriths If we copare the DWT and FFT processing eleent expressions they are realized by siple ultiplication and addition operations. Thus, we can say that DWT can be accoodated in FFT. Thereby, DWT is accoodated in FFT odule to configure a Mutual Module. This configuration of utual odule reduces the power consuption and area required by the two individual systes viz; FFT and DWT on the chip. While, our ipleentation can be further extended to reconfigure and reuse of the available utual odule hardware. Again, we pin-down this reusable and reconfigurable utual odule by realizing DWT in half part (real or iaginary part) execution of the radix-2 cooley-tukey FFT algorith i.e., each odule viz; MCU of DWT, Real part of FFT, Iaginary part of FFT is executed in individual clock cycle. Thus, aking the ipleentation low on throughput rate but reduces area and power consuption. The atheatical expression for reconfigurable and reusable utual odule is presented below. Fro the Fig. 8 we can analyze that the Mutual odule can be still reconfigured by reusing the real part of presented radix-2 FFT butterfly eleent as the iaginary part in next clock cycle: Coparing and A C. A B co*( X 0 X 2). D Cor C D X1 Here we reuse (C + D) _as_a (D - C) in next clock. Where (C + D) contribute to real part of FFT and A (D - C) contributes to iaginary part of FFT. Thus, the reuse and reconfiguration technique is represented in Fig. 9. The lifting DWT and radix-2 FFT butterfly are selected by a select line for the ultiplexers while the 4712 real and iaginary part of fft are executed in 2 clock cycles. Therefore FFT execution require 2 clock cycles. RESULTS AND COMPARISON The experiental results of our proposed ethod are presented below. The proposed design is siulated and synthesized using Xilinx ISE Result for the proposed utual odule obtained are discussed and copared with the individual ipleentation in ters of area and power consued. The logic utilization table for the proposed Mutual odule architecture is shown in the (Table 1 to 4). The coparison table above interprets the logic utilized by the respective architectures of the DWT and FFT with the proposed Mutual odule. If, in an ebedded syste a DWT and FFT architectures of 9/7 filter and 8-point radix-2 butterfly respectively are ipleented then the total area required and power consued by this syste will be very high. This can be clearly recognized fro the coparison table. And hence a Mutual odule is proposed which is reused to perfor both the operations of FFT and DWT instead of ipleenting two different architectures for executing their respective functions. The 9/7 lifting based DWT requires 60 adder/subtractor and 36 ultipliers with total area of 274 slices and power consued is 300 W. And in case of 8-point radix-2 FFT architecture utilizes 108 adder/subtractor and 36 ultipliers in return it consues 315 W power and 228 slices of area. Whereas, the proposed Mutual odule for the DWT and FFT architecture utilizes 9 adder/subtractor, 3 ultiplier and 4 ultiplexers with total area of 81 slices and power consued is 247 W. Therefore, the presented approach proves to be effective and less coplex ipleentation.

8 Table 1: Device utilization table of proposed reconfigurable and reusable utual odel Device utilization suary Slice logic utilization Used Available Nuber of slice LUTs 64 19,200 1 Nuber used as logic 63 19,200 1 Nuber using 06 output only 49 Nuber using 05 output only 14 Nuber used as exclusive 1 route-thru Nuber of route-thrus 15 38,400 1 Nuber using 06 output only 15 Slice logic distribution Nuber of occupied slice 17 4,800 1 Nuber of LUT flip flop pairs 64 used Nuber with an unused flip flop Nuber with an unused LUT Nuber of fully used LUT.FF pairs Utilization (%) Note (s) Table 2: Device utilization table of 9/7 DWT Device utilization suary Slice logic utilization Used Available Nuber of slice LUTs ,200 1 Nuber used as logic ,200 1 Nuber using 06 output only 208 Nuber using 05 output only 1 Nuber using 05 and 06 3 Nuber of route-thrus 4 38,400 1 Nuber using 06 output only 1 Nuber using 05 output only 3 Slice logic distribution Nuber of occupied slices 62 4,800 1 Nuber of LUT flip flop pairs 212 used Nuber with an unused flip flop Nuber with an unused LUT Nuber of fully used LUT.FF pairs Utilization (%) Note (s) Table 3: Device utilization table of 8-ponit FFT Device utilization suary Slice logic utilization Used Available Nuber of slice registers 64 19,200 1 Nuber used as flip flops 64 Nuber of slice LUTs ,200 1 Nuber used as logic ,200 1 Nuber using 06 output only 176 Slice logic distribution Nuber of occupied slices 52 4,800 1 Nuber of LUT flip flop pairs 176 used Nuber with an unused flip flop Nuber with an unused LUT Nuber of fully used LUT.FF pairs Nuber of unique control sets 1 Utilization (%) Note (s) Table 4: Logic coparison table Paraeters 9/7 2D-DWT 8-point FFT Proposed utual odule Adder/subtractor Multiplers Mux Total area Total power@100 MHz 300 W 315 W 247 W Total power@200 MHz 318 W 387 W 250 W CONCLUSION In this study Reconfigurable and reusable coon operator based paraeterization technique is approached which takes advantage of the utual odules present in the two distinct algoriths popularly used in the Ebedded Digital Signal Processing systes applications. A coon operator for the DWT and FFT algoriths is proposed. The Reconfigurable and Reusable Mutual odule approach presents considerably low hardware coplexity, reduced area and power consuption. This approach is perfored over 9/7 DWT and 8-point FFT syste under test achieves alost 60% of reduction in power consuption and for the sae syste under test the area reduced is 84%. REFERENCES Alaus, L., D. Noguet and J. Palicot, A coon operator bank to resolve scheduling issue on a coplexity optiized SDR terinal. Proceeding of 6th Advanced International Conference on Telecounications (AICT, 2010), pp: Alaus, L., J. Palicot, C. Roland, Y. Louet and D. Noguet, Proising technique of paraeterization for reconfigurable radio, the coon operators technique: Fundaentals and exaples. J. Signal Process. Sys., 62(2): Al Ghouwayel, C., Haj-Ali, Z. El-Bazzal and Y. Loüet, Towards a triple ode coon operator FFT for software radio systes. Proceeding of 19th International Conference on Telecounication (ICT, 2012), pp: 1-6. Cooley, J.W. and J.W. Tukey, An algorith for the achine calculation of coplex Fourier series. Math. Coput., 19(90): Gul, S.T., C. Moy and J. Palicot, Two scenarios of flexible Multi-standard architecture designs using a ulti-granularity exploration. Proceeding of the IEEE 18th International Syposiu on Personal, Indoor and Mobile Radio Counications, pp: 1-5. Naoues, M., L. Alaus and D. Noguet, A coon operator for FFT and viterbi algoriths. Proceeding of the 13th Euroicro Conference on Digital Syste Design: Architectures, Methods and Tools, pp: Naoues, M., L. Alaus, D. Noguet and Y. Louët, 2011b. A coon operator for FFT and FEC decoding. Microprocess. Microsy., 35(8): Naoues, M., D. Noguet, Y. Louët, K. Grati and Ghazel, 2011a. An efficient flexible coon operator for FFT and viterbi algoriths. Proceeding of IEEE 73rd Vehicular Technology Conference (VTC, Spring), pp: 1-5. Takala, J. and P. Konsta, Scalable FFT processors and pipelined butterfly units. J. VLSI Sig. Proc. Syst., 43(2-3): Tseng, P.C., C.T. Huang and L.G. Chen, VLSI ipleentation of shape-adaptive discrete wavelet transfor. Proceeding of SPIE 4671, Visual Counications and Iage Processing, pp: