Capacitor Voltage Balancing Control for a Modular Matrix Converter

Transcription

1 pitor Voltge lning ontrol for Modulr Mtrix onverter S. ngkititrkul nd R. W. Erikson olordo Power Eletronis enter University of olordo oulder, O , US ngkitis@olordo.edu strt This pper desries simplified pitor voltge lning sheme for modulr mtrix onverter operting in two-level swithing mode. The proposed sheme is sed on the onventionl spe vetor modultion tehnique. y using two dditionl spe vetors hving opposite diretion, the proposed ontroller is le to regulte ll nine pitor voltges in the onverter. Lypunov-sed ontrol lgorithm gurntees stility. This pper lso inludes experimentl wveforms nd dt to verify the proposed ontrol sheme. The ontrol sheme n e implemented for rel time ontrol using miroproessor nd FPGs. I. INTRODUTION modulr mtrix onverter ws proposed in [1] s novel three-phse to three-phse onverter for vrilespeed wind turine pplitions. gol of this pproh is to hieve high effiieny over wide rnge of operting points, espeilly t low wind speed where typil wind turine systems operte most of the time. The si onverter onfigurtion is shown in Fig. 1. The onverter onsists of nine modulr H-ridge pitor-lmped swith ells, s illustrted in Fig. 2, onneted from eh input phse to eh output phse. This onverter differs from the onventionl mtrix onverter in tht it n uk or oost the voltge, nd indutive filters re employed t oth the input nd output terminls. The terminl voltges of the onverter re synthesized from the pulse width modultion of swith ell pitor voltges, through the swithing of devies in eh H-ridge swith ell. Similr to other onverters tht employ multi-level swithing nd multiple pitors, it is neessry tht ll pitor voltges in the modulr mtrix onverter e stilized nd lned. The single pitor ontrol sheme ws proposed in [2], whih theoretilly stilizes ll nine pitor voltges y keeping hrge lne on the single pitor employed in eh swithing period. However, this ontrol sheme n involve only one pitor in eh swithing period, nd lone is not le to regulte ll pitor voltges in the onverter. pitor voltge lning is omplex prolem for ny multilevel onverter. generl use of the prolem is tht different urrents flow through pitors during onverter opertion. Mny pitor voltge lning shemes hve een proposed for the multilevel d-link onverter y using dditionl ontrol shemes [3 5] or uxiliry iruits [6]. Fig. 1. N i i i Three-phse system 1 (input) i i i Three-phse system 2 (output) si onfigurtion of modulr mtrix onverter D 1 D 2 Q 1 Q 2 D 3 D 4 Q 3 Q 4 n This work ws supported in prt y the DOE Ntionl Renewle Energy Lortory under ontrt no. XX Fig. 2. H-ridge pitor-lmped swith ell.

2 In the modulr mtrix onverter, the primry soure of disturne to the pitor voltge rises from energy stored in the stry indutnes of the wiring interonneting swith ells. During ded-time intervl of the on-tooff stte trnsitions of eh swith ell, the energy from the stry wiring indutne is trnsferred into the swith ell pitor, nd hrges the pitor. This effet of stry indutne on pitor voltge is dependent on the lod urrent nd the swithing frequeny of the onverter. The pitor voltge lning sheme proposed in this pper is sed on the onventionl spe vetor modultion tehnique. y using two dditionl spe vetors hving equl mgnitude nd opposite phse, two dditionl pitors n e hrged nd dishrged during eh swithing period. The two opposite spe vetors prtilly reple the null-stte spe vetor in the onventionl spe vetor modultion; hene, the verge terminl voltges re not ffeted y the proposed lning sheme. The ontrol sheme selets the pitors hving the lrgest positive nd the lrgest negtive error voltges to e regulted in eh swithing period. s result, the voltge errors of the remining pitors re ounded y the two extreme voltge errors. The ontroller uses these errors to derese towrds zero, whih gurntees the stility of the proposed pitor voltge lning sheme. This pper douments the proposed pitor voltge lning sheme long with mesured wveforms nd dt. The proposed ontrol sheme ws implemented in Xilinx Virtex-II PRO hip, whih onsists of PowerP miroproessor nd field progrmmle gte rrys. The proposed pitor voltge lning sheme nd the spe vetor modultion re lulted in rel time y the PowerP miroproessor. The FPGs perform s D ontroller iruits nd pulse width modultion iruit. II. PITOR VOLTGE LNING SHEME. Spe Vetors Employed in Two-Level Swithing modulr mtrix onverter with si onverter onfigurtion is le to generte seven spe vetors tht re employed in the two-level swithing mode: null-stte spe vetor nd six spe vetors with mgnitude of 2V p / 3 [2]. These seven spe vetors form hexgon s illustrted in Fig. 3. The spe vetor digrms for oth sides of the onverter re independent of eh other. Note tht, in the modulr mtrix onverter, the urrent through ny single pitor in eh swithing devie omintion depends solely on the input-side nd the output-side spe vetors, nd not on the other detils regrding the speifi swith stte of the onverter. In (-V p,+v p,0) (-V p, V p /Ö3) (-V p,0,+v p ) (-V p, -V p /Ö3) q-xis (0,+Vp,) (0,2V p /Ö3) w v ref (0,-V p,+v p ) (0,-2V p /Ö3) (V,V,V ) (V d,v q ) (+V p,0,-v p ) (V p, V p /Ö3) d-xis (+V p,-v p,0) (V p, -V p /Ö3) Fig. 3. Seven spe vetors otined from the modulr mtrix onverter in two-level swithing mode. other words, for redundnt swith omintions tht generte identil terminl voltges, the urrent through pitor employed in eh redundnt swith omintion is lso the sme. n exmple of redundnt swith omintions tht generte V = V p, V =0V, V =+V p, nd V = V = V =0V re shown in Fig. 4. In the first omintion, urrent I flows through the pitor, the pitor in the swith ell onneted etween the input phse nd the output phse. pitors nd lso hve urrent I flow through in the seond nd the third omintion, respetively. Fig. 4. V = Vp V = Vp V = Vp Phse V = Phse V = 0V Phse Phse V = Phse V = 0V Phse Phse V = Phse V = 0V Phse Phse V = 0V Phse V = 0V Phse Phse V = 0V Phse V = 0V Phse Phse V = 0V Phse V = 0V Phse V = 0V V = 0V V = 0V n exmple of redundnt swithing omintions.

3 Tle I summrizes the input urrent through pitor employed to generte input-side spe vetors. The effet of the output-side spe vetor on the urrent through the pitor is nlogous. TLE I INPUT URRENTS THROUGH PITOR FOR EH INPUT-SIDE SPE VETOR. Input spe vetor urrent (V p,v p/ 3) I (0, 2V p/ 3) I ( V p,v p/ 3) ( V p, V p/ 3) I I (0, 2V p/ 3) I (V p, V p/ 3) I It n e notied from Tle I tht for ny opposite spe vetors, the urrents through pitors lso flow in opposite diretions, independent of the speifi hoie of pitors. y using two opposite spe vetors with the sme duty yle to prtilly reple the null-stte spe vetor otined from the onventionl spe vetor modultion tehnique [7], two dditionl pitors n e hrged nd dishrged in eh swithing period with minimum effet on the verge terminl voltges.. Modified Spe Vetor Modultion With the modified pproh for the pitor voltge lning sheme, the spe vetor modultion t eh side of the onverter n involve up to five spe vetors: null-stte spe vetor, two djent spe vetors (similr to the onventionl spe vetor modultion), nd two opposite spe vetors. Figure 5 shows the digrm of the modified spe vetor modultion tehnique. Spe vetor is the null-stte spe vetor. Spe d V x d k Fig. 5. f d l d V y v ref 60 o Modified spe vetor modultion. vetors nd re two djent spe vetors to the referene spe vetor, v ref. Spe vetors V x nd V y re ny two opposite spe vetors. The referene spe vetor v ref n e expressed s: v ref = d k + d l + d 0 + d V x + d V y d 0 =1 d k d l 2d (1) where d k nd d l re the duty yles for the spe vetors nd, respetively, whih n e otined from the onventionl spe vetor modultion. d is the duty yle of the opposite spe vetors. The two opposite spe vetors nd the null-stte spe vetor ontriute zero verge to ll line-line voltges. For simpliity of the ontrol, the duty yles of the opposite spe vetor pplied to the spe vetor modultion for oth sides of the onverter re equl. s result, with the modified spe vetor modultion, eh swithing period n hve mximum of seven suintervls tht hve different omintions of input-side nd output-side spe vetors. In the onventionl spe vetor modultion tehnique, eh swithing period n hve mximum of five suintervls, s illustrted in Fig. 6. The two dditionl suintervls generted from opposite spe vetors t oth input- nd output-sides re prtilly repled the suintervl where the nullstte spe vetors t oth input- nd output-sides re generted in the onventionl spe vetor modultion. Input side Output side Input side Output side V d T s d T s V Swithing Pttern for the onventionl SVM -V d T s d T s V n d n T s Opposite spe vetors -V V n } } d n T s dlts dlts +DQ -DQ DQ = 0 Use the pitor Use the pitor with minimum voltge with mximum voltge T S V m dmts V m dmts d k T s Swithing Pttern for the modified SVM Opposite spe vetors d k T s Use the pitor from single pitor ontrol sheme Fig. 6. Spe vetor ptterns in eh swithing period with the onventionl nd the modified spe vetor modultions.

4 With given input-side nd output-side spe vetors in the dditionl suintervls, the urrents through pitors employed in those suintervls n e determined regrdless of the pitors. Note tht for given omintion of input- nd output-side spe vetors, some pitors nnot e employed. Sine the opposite spe vetors re employed in two dditionl suintervls, the urrents through pitors during those suintervls lso flow in the opposite diretion. The ontrol sheme must e le to employ the pitor ording to the urrent in eh dditionl suintervl. When the opposite spe vetors re pplied to the spe vetor modultions for oth sides of the onverter, ny two of the nine pitors n e seleted for regulting during eh swithing period. s result, the modulr mtrix onverter n involve up to three pitors during eh swithing period. While the two pitors re regulted in the first two suintervls, pitor employed in the remining suintervls, whih n e seleted with the single pitor ontrol sheme [2], experienes no net hnge in hrge.. Determintion of two opposite spe vetors The purpose of the pitor voltge lning sheme is to drive ll pitor voltges to sme vlue, whih is the verge of ll nine pitor voltges. Therefore, eh pitor voltge is defined s: V p = V p vg +ˆv p (2) where V p vg is the verge of ll nine pitor voltges, nd ˆv p is the error of the pitor voltge from the verge vlue. y using two opposite spe vetors, two pitors n e regulted during swithing period. Two pitors hving the mximum positive nd mximum negtive error voltges re seleted to e dishrged nd hrged, respetively. The remining pitor error voltges re unhnged, nd ounded y these two voltges. It n e shown tht, for ny given omintion of the two pitors, set of two opposite spe vetors n e found tht llows the desired pitors hrging nd dishrging. Our ontrol implementtion stores this dt in lookup tle. Seletion of two from the nine pitors to e regulted during eh swithing period provides 36 possile omintions. In ddition, there re four or five sets of opposite spe vetors for eh omintion of two pitors. In this pper, opposite spe vetors re seleted from omintion tht provides lrgest urrent mgnitude through the pitor, nd hene the highest gin. This voids the sturtion of the ontrol sheme y regulting pitor with smll (ner zero) mgnitude urrent. For exmple, ssume tht the pitors nd hve mximum negtive nd mximum positive error voltges, respetively. Figure 7 shows swithing devie omintions tht involve oth pitors. The swithing devie omintions in the left olumn involve pitor, while those in the right olumn involve the pitor. The terminl voltges generted from the swithing devie omintions in eh row re opposite to eh other; hene, so do the urrents through pitors nd. The swithing devie omintion in the top left olumn genertes the inputside spe vetor (V p,v p / 3) nd the output-side spe vetor (0, 2V p / 3) with the urrent (I I ) flowing through the pitor. When the input-side spe vetor is ( V p, V p / 3) nd the output-side spe vetor is (0, 2V p / 3), then urrent ( I + I ) flows through pitor. Note tht the opposite terminl voltges n lso e generted y onneting the pitors in the opposite diretion. If the urrent (I I ) hs positive vlue, then the swithing devie omintion on the top left olumn of (1) (2) (3) (4) (5) +Vp +Vp +Vp +Vp- +Vp Vp +Vp +Vp +Vp +Vp +Vp- +Vp- + +Vp- +Vp +Vp + +Vp +Vp Fig. 7. Exmple of swithing devie omintions involve pitors nd.

5 Fig. 7 n e employed to hrge the pitor, nd the omintion on the right olumn n e employed to dishrge the pitor. However, if the urrent (I I ) hs negtive vlue, then pitors nd n e hrged nd dishrged y using the sme omintions ut onneting the pitors in the opposite diretion. Knowing the pitor error voltge (ˆv), nd urrent (I) determined from the spe vetors, the duty yle d of the opposite spe vetors n e otined from d = ˆv (3) T s I where T s is the swithing period of the onverter. lthough the mximum positive nd the mximum negtive error voltges in generl hve different mgnitudes, either n e employed in Eq. (3). D. pitor Voltge Stility The idel pitor wveforms for the proposed pitor voltge lning sheme re illustrted in Fig. 8. During the first two suintervls, the pitors hving the mximum positive nd negtive error voltges re driven towrd the verge pitor voltge, nd then sty unhnged for the remining suintervls. The voltges of the remining pitors re unhnged throughout the swithing period, even though there re voltge ripples in the voltge of the pitor employed in the remining suintervls of the swithing period. s desried in the previous setion, the ontrol sheme n hrge nd dishrge ny two pitors during eh swithing period. In ddition, with the pitor voltges defined s in Eq. (2), there re lwys pitors pitor voltges verge V p V p1 V p2 V p8 V p9 pitor from single pitor ontrol shme [n]ts [n+1]ts t Fig. 8. The idel pitor voltge wveforms for the proposed pitor voltge lning sheme. with positive nd negtive error voltges. The stility of the pitor voltge n e proved y Lypunov s pproh. Lypunov funtion is hosen to e L = 9 j=1 1 2 ˆv2 j 0 (4) where ˆv j is the error voltge of pitor j. With the sme pitne for ll nine swith ells, Eq. (4) n e expressed s L = 1 2 [ˆv2 n +ˆv2 p + ] 0 (5) where ˆv p is the mximum positive error voltge, nd ˆv n is the mximum negtive error voltge, smpled t the eginning of the swithing period. The other terms re the error voltges of the remining pitors. For the lgorithm illustrted in Fig. 8, we n ompute the hnge in L over one swithing period. When the duty yle d is omputed s in Eq. (3) using ˆv =ˆv p, then the error voltge ˆv p is redued to zero fter one swithing period nd the orresponding hrge is trnsferred to the pitor ssoited with ˆv n. The hnge in L is then equl to ΔL = 1 2 [(ˆv p +ˆv n ) 2 ˆv n 2 ]+1 2 [0 ˆv2 p ] (6) = ˆv pˆv n Sine ˆv p is lwys positive nd ˆv n is lwys negtive, ΔL of Eq. (6) is lwys negtive. Hene, Lypunov s stility theorem implies stility of this ontrol lgorithm. In prtie, feedk loop for regulting the verge pitor voltge is neessry when the modulr mtrix onverter is interfed etween genertor nd n infinite-us utility. Modeling nd design of the ontrol system for regulting the line urrents nd the verge pitor voltge is treted in [8]. III. EXPERIMENTL RESULTS To verify the proposed ontrol sheme, the ontrol sheme hs een implemented for lortory prototype. The lok digrm of the lortory prototype is illustrted in Fig. 9. The ontrol sheme ws implemented using Xilinx Virtex-II PRO X2VP4, whih onsists PowerP 405 miroproessor nd field progrmmle gte rrys (FPGs). The PowerP miroproessor is operted t 300 MHz. The mjor tsks of the PowerP miroproessor re to perform the spe vetor modultions nd the pitor voltge lning sheme. The FPG prt ontrols the D iruits nd the PWM iruit.

6 + + + N 12-it D (D9220) nlog Multiplexer (MX306) Sensing iruits V LL,I i i i PowerP D ontrol iruit PWM ontrol iruit 12-it D (D9220) Lookup Tle (T49LV040) nlog Multiplexer (MX306) Opto-isolted Gte Driver iruits Differentil mp iruits V p i i i V LL,I n Three-phse resistive lod Virtex II PRO Fig. 9. lok digrm of the lortory prototype. For the power stge, IGTs with nti-prllel diodes re used s swithing devies. The six indutors for the input nd output phses hve indutnes of 1.2 mh. Eh swith ell hs 9.4 µf polypropylene pitor. The onverter is operted t swithing frequeny of 20 khz. For omprison, Fig. 10 shows pitor voltge wveform nd 30 Hz output PWM line-line voltge wveform generted without the pitor voltge lning sheme. Figure 11 shows the sme pitor voltge nd 30 Hz output PWM line-line voltge wveforms with the pitor voltge lning sheme t the sme operting point. The ddition of opposite spe vetors n e notied in the PWM line-line voltge wveform. Figure 12 illustrtes the output 30 Hz line-line voltge wveform fter low-pss filtering, long with pitor voltge wveform. Figure 13 shows omprison of two pitor voltge wveforms. It n e seen tht regultion of ±10% is hieved. Fig. 10. Wveforms of pitor voltge nd n output PWM line-line voltge without pitor voltge regultion. Fig. 11. Wveforms of pitor voltge nd n output PWM line-line voltge with pitor voltge regultion.

7 new pitor voltge lning sheme is proposed for the modulr mtrix onverter operting in the twolevel swithing mode. The ontrol sheme is sed on the onventionl spe vetor modultion. y using two dditionl spe vetors hving the sme mgnitude ut opposite diretion, two dditionl pitors n e hrged nd dishrged during eh swithing period. The ontrol sheme hs minimum effet on the verge voltge; however, it inreses the terminl voltge ripple. Stility of the lgorithm is proven y Lypunov pproh. The ontrol sheme hs een implemented using miroproessor nd FPGs, whih proves tht the proposed sheme is prtil for rel time ontrol. The omplexity of the ontrol sheme is softwre issue, whih n e implemented in single hip I without dditionl iruitry. The results demonstrte the fesiility of the lning the pitor voltges of omplex system ontining nine independent onverter modules. REFERENES Fig. 12. Wveforms of pitor voltge nd filtered output line-line voltge. [1] R. W. Erikson nd O.. l-nseem, New Fmily of Mtrix onverters, IEEE Industril Eletronis Soiety nnul onferene, vol. 2, pp , Nov./De [2] S. ngkititrkul nd R. W. Erikson, ontrol nd Implementtion of New Modulr Mtrix onverter, IEEE pplied Power Eletroni onferene, vol. 2, pp , Fe [3] G. Sinh nd T.. Lipo, Four-Level Inverter sed Drive with Pssive Front End, IEEE Trns. on Power Eletronis, vol. 15, pp , Mr [4] F. Z. Peng, J. S. Li, J. MKeever, nd J. Vnoevering, Multilevel Voltge-Soure onverter System with lned D Voltges, IEEE Power Eletroni Speilist onferene, vol. 2, pp , Jun [5] N. elnovi nd D. oroyevih, omprehensive Study of Neutrl-Point Voltge lning Prolem in Three-Level Neutrl-Point-lmped Voltge Soure PWM Inverters, IEEE Trns. on Power Eletronis, vol. 15, Mr [6] N. S. hoi, J. G. ho, nd G. H. ho, Generl iruit Topology of Multilevel Inverter, IEEE Power Eletroni Speilist onferene, pp , Jun [7] L. Huer nd D. orojević, Spe Vetor Modulted Three- Phse to Three-Phse Mtrix onverter with Input Power Ftor orretion, IEEE Trns. on Industry pplitions, vol. 31, no. 6, pp , Nov./ De [8] K. lmzeedi, Modeling nd ontrol of the urrents nd pitor Voltges of Novel Multilevel Mtrix onverter, Ph.D. disserttion, University of olordo t oulder, Nov Fig. 13. Wveforms of two pitor voltges. IV. ONLUSIONS