Hybrid Optimization of High Performance Cell-Based Design Beyond Flex-Cells in Timing Critical Paths

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1 Hybrid Optimiztion of High Performnce Cell-Bsed Design Beyond Flex-Cells in Timing Criticl Pths Debshis Bhttchry Chief Technology Advisor Zensis Technologies Inc Dell Avenue, Suite #100, Cmpbell, CA Phone: (408) Fx: (408) Zensis TM, Zen TM, ZenTime TM, ZenCell TM, ZenPower TM, Hybrid Optimiztion TM nd ZenAre TM re ll trdemrks of Zensis Technologies Inc. All other trdemrks re the property of their respective owners Zensis Technologies Inc. All rights reserved Pge 1

2 Introduction Automted synthesis-oriented digitl integrted circuit (IC) design methodologies hve revolutionized the semiconductor industry over the pst 25 yers. Historiclly, use of prechrcterized nd silicon verified stndrd cells ws driven by the designers' need to design nd verify lrge digitl circuits using limited resources trnsistor-level design nd verifiction is simply too resource-intensive to be commercilly vible for most digitl designs. Stndrd cells provided reltively fine-grined control over the structure of the digitl circuit, nd yet were menble to mnipultion using utomted synthesis tools tht mde it possible to design multi-million gte ICs with tem of less thn 10 engineers. However, from its inception, qulity of the designs creted by such utomted stndrd-cell bsed design flows, hs been deemed poor to brely cceptble, by lmost ny mesure of qulity including clock speed, re/die-size, power consumption, etc. In series of studies including specil session t the 37th Design Automtion Conference (DAC 2000) [DAC01][DAC02], it ws estimted by vrious reserchers tht designs creted by such utomted design flows re slower by t lest fctor of 6 nd lrger in design re by t lest fctor of 10, when compred to similr designs creted nd/or optimized mnully. It ws shown further tht significnt portion of the deficiency in qulity e.g. qurter or more of the speed shortfll cn be ttributed to the use of fixed, pre-defined librry of stndrd cells. This deficit in qulity hs led to severe timing closure problem tht grows worse with every new process genertion. As fr bck s in 1999, when 180nm process ws still new, surveys done by Collett Interntionl showed tht greter thn 60% of ll ASIC designs hd timing closure problems [COL99]. The problem hs become significntly worse s fbriction processes progressed through 130nm nd 90nm process nodes to 65nm process node of tody. Timing Improvement Techniques Over the yers, vrious forms of mnul intervention nd tweking of designs hve been incorported into utomted design flows. Such prctices include: 1. Use of specilly (usully mnully) crfted mcro-cells, such s specil memories, nd specil functionl blocks like brrel shifters nd multipliers. 2. Use of specil directives in synthesis, to force use of specilly crfted mcro-cells for implementtion of known problem constructs in register trnsfer level (RTL) description of digitl circuits. 3. Specil lyout techniques for structured circuits, e.g. tiling for dtpth circuits. 4. Use of tcticl (design-specific) cells which re similr in size to typicl stndrd cells, s opposed to mcro-cells, which tend to be much bigger tht re creted mnully, bsed on prior experience with similr design, or experience with prior versions of the sme design. 5. Migrting to n dvnced process technology Zensis Technologies Inc. All rights reserved Pge 2

3 In the nnometer design er, high-qulity erly floor plnning nd physiclly wre logic synthesis re essentil to contining the timing closure problem [EET01]. Over the lst five yers, this recognition hs led to incresingly greter integrtion of physicl design cpbilities with trditionl synthesis tools. New design tool suites tht llow mjor design chnges to be mnged t the Register Trnsfer Level (RTL) stge, combined with smller process geometry nd other process dvncements like low-k technology, re lso helpful in chieving trget timing within brely resonble mount of time. Some recent EDA products which mitigte the timing closure problem to some extent, include Synopsys Physicl Compiler nd more recently Synopsys Glxy Design Pltform, Cdence SOC Encounter pltform, Cdence VoltgeStorm nd SignlStorm, nd Alter Qurtus II. Synopsys Physicl Compiler ws successfully employed in the design of lrge designs including vrious grphics processors from nvidi nd the Switching Element SE9 of the Informtion nd Communiction Networks (ICN) division of Siemens [SYN01], to nme few. Synopsys Glxy Design Pltform hs been recently used by Reness in Jpn to tpe out 90-nm SoC design. Cdence VoltgeStorm nd SignlStorm hve been employed by Fujitsu s the stndrd power verifiction nd nnometer dely clcultion solutions for their ASICs [CAD01]. These provide extremely relible nd ccurte metrics for dely nd timing tking into ccount vrious signl integrity issues tht re criticl for UDSM designs. The Alter Qurtus II softwre includes dvnced timing closure fetures with close interction between synthesis, timing nlysis, floor pln editing nd plce-nd-route processes llowing designers blnce multiple constrints, including multiple clocks, routing resources nd re constrints [ALT01]. With continuous push towrds mnging designs t higher levels of bstrction, trnsistor-level circuit design is rpidly becoming dying rt, with hrdwre engineers treting design cretion essentilly like softwre engineering project. This is mply evident in the EDA community's continued focus on utomted design nd verifiction of digitl systems strting with behviorl-level design lnguges like System Verilog nd System C. As result, every design tem fces key dilemm lte in their design cycle when trnsistors cn no longer be ignored: how cn engineers tke into ccount the llimportnt trnsistor-level detils tht ultimtely impct the qulity of their designs, without cusing the design cycle nd tem size to grow drmticlly? Hybrid Optimiztion with Flex-Cells to the Rescue The design community openly cknowledges tht virtully every high-performnce design project tht relies on utomted (synthesis-oriented) design flow, lso uses design-specific tcticl cells which re identified nd creted mnully, nd then utilized in design vi combintion of RTL coding style nd synthesis directives. The quest to overcome the limittions of stndrd-cell bsed design methods, tkes step beyond tcticl cell cretion into the relm of creting new, design nd context-specific cells designted flex-cells during the process of optimizing given digitl design [COM01]. From superficil point of view, flex-cell-bsed design optimiztion utomtes the cretion of tcticl cells, thereby helping to bridge the qulity gp. However, deeper exmintion 2005 Zensis Technologies Inc. All rights reserved Pge 3

4 of the flex-cell-bsed optimiztion process mkes it mply cler tht the full impct of such optimiztion goes fr beyond providing better frmework for creting tcticl cells. This optimiztion process to eliminte timing problems nd improve the performnce of cellbsed designs tht goes hnd-in-hnd with the cretion of flex-cells is designted the hybrid optimiztion technology [CHI01]. An overview of the hybrid optimiztion process for digitl circuits is shown in Figure 1 [COM01]. Figure 1: Overview of hybrid optimiztion process for digitl designs, using flex-cells. The hybrid optimiztion technology opertes on design simultneously t the trnsistor, gte, nd physicl design levels; it cretes new flex-cells, djusts physicl design nd ssesses timing tking physicl design into ccount, in mnner tht is trnsprent to the designer. Consequently, this optimiztion technology reps the benefits of custom-cell crfting, physicl optimiztion, nd plcement-ccurte timing in one unified pltform, thereby opening n entirely new venue for improving cell-bsed designs. In brief, during hybrid optimiztion, plcement-ccurte timing zeros in on the timing rod-blocks in design, the ct of custom-cell crfting breks the rod-blocks by designing new contextspecific cells for criticl prts of the logic, nd physicl optimiztion restructures the physicl nd logicl design of the surrounding circuitry to cpitlize on these locl improvements. Consequently, hybrid optimiztion employing dynmiclly creted flexcells chieves fster timing closure, without imposing ny substntil penlty in power, re, or signl integrity [COM01] Zensis Technologies Inc. All rights reserved Pge 4

5 Hybrid optimiztion with dynmic flex-cell cretion integrtes smoothly into most existing cell-bsed flows. The design specific cells creted on-the-fly use the sme rchitecture s the bsic stndrd cell librry, nd hence, plce-nd-route tools see no difference between bsic stndrd cells nd the new cells generted during optimiztion. As result, no chnge is required to n existing synthesis or physicl design tools when hybrid optimiztion is dded to the design flow. In-Depth Look t Hybrid Optimiztion with Flex-Cell Cretion The digitl IC design optimiztion process shown in Figure 1 is gered towrd enhncing the design's performnce specificlly, incresing clock speed. It employs the timetested mnul process of loclly optimizing digitl design driven by globl timing nlysis. The locl optimiztion step consists of two brod steps designted clustering nd mpping. The clustering process identifies the best cndidte regions in the design for locl optimiztion, nd is driven by results from sttic timing nlysis (STA) pplied to the design globlly. The clustering process yields set of clusters groups of one or more stndrd cells tht must be replced by new flex-cells creted for their respective timing contexts. The mpping process tkes s inputs the clusters nd their respective timing contexts, then determines resonbly smll set of best-cndidte flex-cells which should be used to replce the clusters. The optimiztion control process serches through this set of best cndidte flex-cells to determine whether replcing one or more clusters with flex-cells will improve the given design's overll timing. The close coupling between the STA, clustering, mpping, nd optimiztion control processes is key to success of the hybrid optimiztion technique. Trde-Offs in the Mpping Process The mpping process cn be quite involved. At minimum, it includes the following: ensuring functionl correctness of the resultnt trnsistor-level design; meeting design trgets, including, for exmple, performnce of the generted flexcells, given the timing contexts for their intended use; meeting other implementtion constrints, such s mximum length of N- or P- trnsistor chins in the flex-cells, the required output drive strength for the flex-cells, input cpcitive lod of the flex-cells, nd so on; minimizing the number of trnsistors in the flex-cells, subject to implementtion constrints mentioned bove; sizing the trnsistors in flex-cells, s necessry. Figure 2 shows more detiled view of the mpping process [COM01] Zensis Technologies Inc. All rights reserved Pge 5

6 Figure 2: Flex-cell mpping process detils. Inputs to the mpping process include, t minimum, the following: (i) set of structurl netlists composed of stndrd cells, otherwise known s clusters; (ii) set of performnce constrints for ech individul cluster; nd (iii) importnt process-dependent informtion like SPICE models for trnsistors (developed originlly t UC Berkeley, SPICE is the most widely used simultion tool for trnsistor-level design). Key steps of the mpping process, s shown in Figure 2, include the following: () cretion of trnsistor-level netlist; (b) fst chrcteriztion tht incorportes the flex-cells' implementtion contexts; (c) trnsistor sizing; (d) ccurte but slower chrcteriztion of the finl trnsistor-level netlist; (e) optionl lyout synthesis with trnsistor sizing, vi lyout synthesis tool; (f) prsitic extrction nd ccurte post lyout chrcteriztion if lyout synthesis is performed; nd (g) genertion of views to fit the flex-cells into stndrd-cell-bsed design flow. This process contrsts shrply with conventionl utomted trnsistor-level design optimiztion techniques tht derive their benefits primrily from trnsistor sizing. A vriety of lgorithms nd heuristics re vilble in the literture for genertion of trnsistor netlist given the originl cluster. For exmple, severl techniques for deriving trnsistor netlists use the Binry 2005 Zensis Technologies Inc. All rights reserved Pge 6

7 Decision Digrms (BDDs) [AKE78] representing the function of the cluster, s strting points. A BDD is well-known dt structure bsed on cyclic directed grphs used to represent functions commonly encountered in digitl circuits, nd recently, severl reserchers, including Liu nd Abrhm [LIU99], Gvrilov et l. [GAV97], Newton et l., nd Knecko et l. [KAN98], hve demonstrted techniques to derive trnsistor netlist structures using BDDs. The impct of chnge in trnsistor topology nd trnsistor sizing on the performnce of flex-cell, is complex. Vrious combintions of choices mde in the processes depicted in Figure 2, nd vrious contexts of use, my result in different sets of design-specific flexcells creted for given design. In prticulr, in keeping with modern physicl synthesis flows, the flex-cell cretion process is plcement wre. Hybrid optimiztion typiclly incorportes sophisticted physicl estimtors s well s the bility to djust given plcement, incrementlly, due to chnges in the design netlist. The estimtors nd incrementl plcement cpbilities, re utilized by the optimiztion control process to trck the impct of flex-cells introduced during optimiztion, on timing of the design t hnd. In fct, physicl plcement drives ll the key optimiztion steps, including cell clustering, buffering nd trnsistor sizing. Gte -Level Cluster c d b 4 Cells, 9 nets y Criticl Pth: - > y Rise = 0.26 ns ; Fll = 0.31 ns Before After Rise (-y) 0.26ns 0.12ns Fll (-y) 0.31ns 0.10ns # Cells 4 1 # Trnsistors Pth depth 3 2 # nets 9 7 Design Specific ZenCell 1 Cell, 7 nets Z Criticl Pth: - > y Rise = 0.12 ns ; Fll = 0.10 ns d d b b c c c c y 22 Trnsistors Pth depth = 3 levels ZenTime Criticl Pth: -> y Rise = 0.12 ns; Fll = 0.10 ns c b d d c b d 13 Trnsistors; Pth depth = 2 levels y Tx - Level View of Gte Cluster After Hybrid Optimiztion Figure 3: Flex-cell genertion illustrted: from originl cluster of stndrd cells to flexcell creted by mpping process, nd summry of performnce improvement resulting from replcement of cluster by flex-cell. Figure 3 shows some results of nd uses for the flex-cell genertion process. This digrm shows the flex-cell tht results when cluster of cells in design re mpped to single trnsistor-level flex-cell, with the primry gol being performnce optimiztion. The mpping process strts with the cluster of cells in the upper left hnd corner, which hs only one criticl input highlighted in the digrm. In this context, n input's criticlity is mesured by the dely 2005 Zensis Technologies Inc. All rights reserved Pge 7

8 from this input to the cluster's output, which limits the overll performnce of this cluster. A cndidte flex-cell generted by the mpping process is shown in the lower right-hnd corner; its chrcteristics re summrized in the tble in the digrm. The tble in Figure 3 lso shows the performnce improvement tht would result from replcing the cluster with this flex-cell. Although this description of the mpping process is implicitly focused on the sttic CMOS fmily of logic circuits, if the trget design implementtion uses nother fmily of MOS circuit design including vrious forms of dynmic CMOS, combintion of sttic nd dynmic CMOS, nd so on this mpping process could be pplied brodly to the cretion of NMOS or PMOS networks for such logic fmilies. Flex-Cell Cretion Outside Timing Criticl Regions: Hybrid Optimiztion of Criticl & Sub-Criticl Region Boundry The development of hybrid optimiztion using dynmiclly creted flex-cells hs dded new dimension to the design optimiztion tool rsenl especilly, lte in the design cycle. Although hybrid optimiztion originted with focus on the timing-criticl prts of the design, it hs since been recognized tht optimiztion of sub-criticl portions of the design, especilly sub-criticl portions tht touch the timing criticl portions of the design, holds the key to further improvement in qulity of results ttined by hybrid optimiztion Input Cp Lod = 20ff A Y C1 C2 Y Criticl Region Input Cp Lod = 16ff F1 C2 Y Criticl Region Figure 4: Use of flex-cell in sub-criticl region of design to minimize cpcitive lod on cells in criticl region Zensis Technologies Inc. All rights reserved Pge 8

9 Trnsistor-level optimiztion of input pin cps of such sub-criticl pins t the criticl/subcriticl region boundry is one such key optimiztion trnsformtion tht leds to the cretion of flex-cells outside the timing criticl region of design. The overll concept of this trnsformtion is illustrted in Figure 4. As depicted in Figure 4, this optimiztion reduces some of the spre slck in the offcriticl portion of cell C1 pin A through Y by reducing the sizes, nd consequently, drive strength of the trnsistors connected to pin A of C1, thereby creting new flex-cell F1. However, the reduced sizes of trnsistors in flex-cell F1 led to reduced lod on driver cell C2 which is on the criticl pth, thereby speeding up the dely nd trnsition of ll pths to the output Y of C2. When pplied crefully, in conjunction with other typicl trnsformtions used in hybrid optimiztion technology, ll timing pths pssing through output Y of cell C2 cn benefit from this locl speedup t pin Y of cell C2. Like in the originl hybrid optimiztion methodology, this trnsformtion necessittes trnsistor-level optimiztion of cell C1 beyond wht cn be chieved through gtesizing or pin-permuttion of cell C1 using other functionlly equivlent stndrd cells from the existing librry of cells. The result is the cretion of new flex-cell s prt of the optimiztion process, s in the originl hybrid optimiztion methodology [COM01]. However, unlike the originl hybrid optimiztion methodology, the new flex-cell F1 is not creted directly on ny timing criticl pth of the design. Insted, it is creted in sub-criticl region of the design tht is directly connected to or is driven bycomponents in one or more timing criticl pths of the design. Hybrid Optimiztion Results Results from experimentl studies help to demonstrte the substntil benefits tht cn be derived from using flex cells to custom-optimize both the criticl nd sub-criticl regions of the design, resulting in substntil improvement in performnce lte in the design cycle. The performnce impct of trnsistor-level optimiztion, t the cell level, ws lredy illustrted in Figure 3. In tht cse, the worst-cse dely for n in-cell criticl pth improved from 0.31ns in the conventionl implementtion to remrkble 0.13ns in the flex-cell implementtion. Next, consider how the hybrid optimiztion using flex-cells cn lter design's criticl region profile. The grph in Figure 5 plots the number of pths violting specific timing constrint in two versions of n dder design [COM01]. A stteof-the-rt, commercil, stndrd-cell synthesis tool produced the first design whose criticl pth profile is represented by the outer curve. The second design, whose criticl pth profile is represented by the inner curve, ws obtined by pplying hybrid optimiztion to 2005 Zensis Technologies Inc. All rights reserved Pge 9

10 Figure 5: Impct of flex-cell-bsed hybrid optimiztion on criticl region of n dder. the originl design. Figures 5 demonstrtes quite clerly tht use of flex-cells llowed for significntly better optimiztion of the criticl region, leding to substntilly smller number of pths violting the given timing constrint. A summry of results from ppliction of hybrid optimiztion using flex-cells to set of industril designs, tht rnge from 7,000 plceble instnces nd pproximtely 30,000 gtes to roughly 80,000 plceble instnces nd pproximtely 320,000 gtes, is shown in Tble 1. Clerly, use of flex-cell-bsed hybrid optimiztion methodology cn chieve performnce enhncements rnging from 10 to 18 percent. Design Initil Number of Instnces Number of unique flex cells dded Initil Clock Frequency Finl Clock Frequency Performnce Improvement (percent) Runtime (CPU hours) CKT1 7, CKT2 18, CKT3 33, CKT4 38, CKT5 80, Tble 1: Industril design optimiztion using flex-cell-bsed hybrid optimiztion; new flex-cell cretion restricted to criticl regions of the design only Zensis Technologies Inc. All rights reserved Pge 10

11 Figure 6: Plot of worst slck improvement vs time with nd without cretion of new flex-cells in sub-criticl regions of design being optimized. Enbling the cretion of new flex-cells in sub-criticl regions of design to minimize the cpcitive lod seen by cells in the criticl regions, without ffecting drive-strengths of cells in the criticl region llows hybrid optimiztion to chieve even greter performnce improvement thn those presented in Tble 1. This is illustrted in Figure 6 with plot of the improvement in worst slck over time for CKT3, during hybrid optimiztion in two modes with nd without use of flex-cells in sub-criticl region enbled. Clerly, enbling cretion of new flex-cells in sub-criticl regions during hybrid optimiztion leds to noticeble overll gin in performnce improvement. In the plot of Figure 6, the immedite performnce gin from such cretion of new flex-cells in sub-criticl regions, is highlighted in color red. A creful exmintion of Figure 6 leds nturlly to the following conclusions: (i) the immedite performnce gin from cretion of new flex-cells in sub-criticl regions, is firly smll; (ii) cretion of new flex-cells in sub-criticl regions clerly help remove some locl minim, which llows the overll optimiztion to progress much further thn is possible otherwise; (iii) when cretion of new flex-cells in sub-criticl regions is enbled, run times cn be long. However, user hs the choice of trding off runtime versus gin in performnce, bsed on prcticl considertions Zensis Technologies Inc. All rights reserved Pge 11

12 Flex-Cell-Bsed Optimiztion Benefits In summry, custom design techniques chieve the best performnce when doing digitl designs, nd will continue to do so in the foreseeble future. However, for mny pplictions, utomted ASIC design methodology is the only prcticl choice. Flex-cellbsed hybrid optimiztion is collection of techniques borrowed from custom design method nd dpted to the needs of ASIC design methodology: it focuses on utomted trnsistor-level optimiztion, nd represents vible extension of the current ASIC design methodology. Some key benefits of this pproch re: Improvement in design performnce by over 15% by tightening negtive-slck pths in criticl pths without incurring ny substntil re or power penlty. Fster timing closure thn wht is possible with existing ASIC design tools, especilly, lte in the design cycle. Ability to utilize existing cell-bsed flows nd high yield technology nodes without cusing ny increse in die-size or power. Ability to pply methodology t vrious points in cell-bsed ASIC flow byugmenting, rther thn replcing ny of the trditionl design tools. The methodology cn be used fter synthesis to optimize smll blocks using wirelod estimtes. The methodology cn lso be used fter plcement of lrge blocks, by importing plcement nd post-route timing nnottions into ZenTime [EDN02]. Finlly, crefully chosen prts of the methodology (e.g., trnsistor-level sizing) cn be used fter clock-tree synthesis (CTS), to perform very lte-stge clenup without disturbing the sequentil elements or the clock tree itself Zensis Technologies Inc. All rights reserved Pge 12

13 References: [AKE78] Akers, S.B., Binry Decision Digrms, IEEE Trnsctions on Computers, June 1978, pp [ALT01] [CAD01] [COL99] Collett Interntionl, 1999 IC/ASIC Functionl & Timing Verifiction Study. [DAC01] Chinnery, D.G., nd Keutzer, K., Closing the Gp Between ASIC nd Custom: An ASIC Perspective, Proceedings of the 37 th Design Automtion Conference, June 2000, pp [DAC02] Dlly, W.J, nd Chng, A., The Role of Custom Design in ASIC Chips, Proceedings of the 37 th Design Automtion Conference, June 2000, pp [EDN01] Zensis: EDA s Next Genertion, Electronic News, April 29, [EDN02] Tool Tightens Timing in ASICs Criticl Pths, Electronic Design, My 12, [EET01] Mking Pece with the Timing Closure Gp, EE Times, My 12, [GAR01] Grtner Dtquest, EDA tkes brief detour before the min rod, EE Times, June 30, [GAV97] Gvrilov, S., et l., Librry-less Synthesis for Sttic CMOS Combintionl Logic Circuits, Proceedings of the Interntionl Conference on Computer-Aided Design, November 1997, pp [KAN98] Kneko, M., nd Tin, J., Concurrent Cell Genertion nd Mpping for CMOS Logic Circuits, Proceedings of the Asi-South Pcific Design Automtion Conference, Jnury 1993, pp [LIU99] Liu, C.P., nd Abrhm, J.A., Trnsistor-Level Synthesis for Sttic Combintionl Circuits, Proceedings of the 9 th Gret Lkes Symposium on VLSI, 1999, pp [SYN01] [EED01] Zensis Technologies Inc. All rights reserved Pge 13

14 [CHI01] Chinnery, D. nd Keutzer, K., Closing the Gp between ASIC & Custom, Kluwer Acdemic Publishers, [COM01] Roy, R., Bhttchry, D. nd Boppn, V., Trnsistor-Level Optimiztion of Digitl Designs with Flex Cells, IEEE Computer, 2005, pp Zensis Technologies Inc. All rights reserved Pge 14